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RAM in an SSD context

flash and nvm
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hybrid DIMMs
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DIMM wars in SSD servers - Memory1?
are you ready to rethink enterprise DRAM architecture?
nvRAMs - state of the semiconductor market readiness

Editor:- September 17, 2015 - Gaps in the memory hierarchy have created openings for new types of memory is a new blog by Mark LaPedus, Executive Editor - Semiconductor Engineering - which is flavored with some strong opinions from leading memory analysts.

Mark says - "after numerous delays, a new wave of next-generation, nonvolatile memories are finally here. One technology, 3D NAND, is shipping and gaining steam. And 3 others - Magnetoresistive RAM, ReRAM and even carbon nanotube RAMs - are suddenly in the mix." the article

Diablo aims to shrink enterprise DRAM market with flash as memory

Editor:- August 12, 2015 - Diablo has launched an assault on the enterprise server RAM market with the launch of a new DRAM compatible emulation memory module called "Memory1" which replaces DDR-4 DRAM - with byte addressable flash.

In a new blog on - DIMM wars in SSD servers - how significant is Diablo's Memory1? I discuss the potential impact of this technology and make some guesses about how Diablo has managed to replace DRAM with flash. the article

data compression techniques in memory systems

Editor:- May 26, 2015 - Inside the SSD controller brain the compressibility of data is one of the tools which can go into the mix of optimizing performance, endurance and competitive cost.

A recent paper - A Survey Of Architectural Approaches for Data Compression in Cache and Main Memory Systems by Sparsh Mittal and Jeffrey S. Vetter in IEEE Transactions on Parallel and Distributed Systems - reviews the published techniques available and places their relevance in the context of real and future memory types and applications. The survey covers applications from embedded systems upto supercomputers. In addition to being useful resource directory of related papers the article gives you a brief description of many compression techniques, where you might use them and what benefits you might expect.

See also:- list of articles and books by Sparsh Mittal which among other things covers caching techniques, reliability impacts and energy saving possibilities in a wide range of server architectures.

flash backed DIMMs - a new directory from

Editor:- October 21, 2014 - Although has been writing about flash backed DRAM DIMMs since the first products appeared in the market - I didn't think that subject was important enough before to rate a specific article or market timeline page. (Unlike memory channel SSDs - which became 1 of the top 10 SSD subjects viewed by readers after having had its own directory page since April 2013).

However, sometimes a market is defined as much by what it isn't as by what it is.

And so - to help clarify the differences between these 2 types of similar looking storage devices (one of which I think is much more significant than the other - but both of which are important for their respective customers) I have today created a directory page for hybrid DIMMs etc - which will act as the future pivoting point for further related articles.

Samsung in volume production of 3D DDR4 RDIMMs

Editor:- August 27, 2014 - Although the main interest in DDR4 RDIMMs - from an SSD market perspective - will be in how that interface opportunity gets leveraged in future memory channel flash SSDs - let's not forget that the motherboard slots - which will enable that market - have been designed for DRAM. So the DRAMs will come first and are an important part of the countdown to the new DDR4 flash DIMM ecosystem.

In that context I'd like to mention that Samsung is today celebrating "a new milestone in the history of memory technology" with the announcement that the company is in volume production of the industry's first 64GB DDR4 RDIMMs (DRAM) that use 3D "through silicon via" (TSV) stacked die package technology and 20nm class die geometries.

Samsung says that the new 64GB TSV module performs 2x as fast as a 64GB module that uses conventional wire bonding packaging, while consuming approximately 1/2 the power.

Editor's comments:- Samsung describes this announcement as "historic" and I was content to include that positioning statement in the news above - because much of what Samsung has done in the past has indeed had historic significance.

For more examples - see "Samsung historic" which gives you search results from the news archives.

Diablo unveils DDR-4 flash DIMM SSDs

Editor:- August 7, 2014 - Diablo yesterday announced details of a new 2nd generation memory channel SSD - low latency flash SSD accelerators in DDR-4 sockets - which will sample to oems in the first half of 2015.

Along with the new hardware technology there will be an improved software platform - with features like NanoCommit - which Diable says will enable hundreds of millions of transactions per second, with nanosecond latency.

Editor's comments:- After FMS - Diablo sent me more info (pdf) about their FMS presentation (pdf) from which I have extracted these key features.
  • Diablo's converged memory architecture (flash tiered with DRAM) is planned to support 700 million random cachelines / sec.
  • Latency of each cacheline is about 48 nanoseconds.
  • Diablo's NanoCommit supports byte addressable small writes to flash with high transaction rates and the ability to mirror the DRAM contents to persistent storage.
  • The combination of technologies would enable something like a 1U server with 25TB of converged memory.
Diablo MCS - nanocommit - click for pdf

AgigA Tech samples 1st DDR4 NVDIMM

Editor:- August 6, 2014 - AgigA Tech today announced that it is now sampling the industry's first DDR4 Nonvolatile DIMM (NVDIMM) to key OEMs and development partners.

is there a market for I'M Intelligent Memory inside SSDs?

Editor:- June 4, 2014 - Are there applications in the SSD market for DRAM chips which integrate ECC correction inside the RAM chip - and which plug into standard JEDEC sockets?

That was the question put to me this afternoon by Thorsten Wronski - whose company MEMPHIS Electronic AG distributes I'M Intelligent Memory in Europe.

Thorsten told me he's had a good reaction from the SSD companies he's spoken to - which is why he phoned.

But in a long conversation about the economics and architectures of end to end error correction in SSDs and the different ratios of RAM cache to flash in SSDs - I told him that my initial reaction was he should look at embedded applications - which depend on the reliability of a single SSD - rather than enterprise systems in which the economics analysis for arrays point to a system wide solution rather than a point product fix.

The interesting thing is he said he's done tests on the new I'M memory as drop in replacements for unprotected memory designs- in which he accelerated the likely incidence of error events by increasing the interval between refreshes and raising the temperature.

Here's what he said.

"We assembled a standard 1GB unbuffered DIMM with 8 chips of 1Gbit ECC DRAM. Then we put this into a test board and ran RSTPro (a very strong memory test software). No error found.

Next we put the whole board into a temperature chamber at 95°C, which normally requires the refresh rate to be doubled (32mS instead of 64mS). No error found.

Finally we wrote a software to change the refresh-register of the CPU on the board, so we were able to set higher values. The highest possible was 750mS, so the DRAM did almost not get any more refreshes. Still it continued working in RSTPro without a single error for 24 hours.

We tried the same with Samsung and Hynix modules, but none of them came even close to those results. Most failed at refresh-rates of 150 to 200 mS, which is not bad indeed. Many more tests will follow."

Editor's comments:- the reason I mention this - is because adapting the refresh rate was one of the things mentioned in my recent blog - Are you ready to rethink RAM?

However - most of the leading SSDs in industrial markets don't have RAM caches for other reasons (to reduce the physical space, power consumption, hold-up time, or because don't need the performance). So I told Thorsten I don't see an industry wide demand inside SSDs. But some of you might already have thought of applications.

See also:- I'M ECC DRAM product brief (pdf)

big memory makers still need to recoup investments in flash and DRAM before switching to newer technologies

Editor:- May 22, 2014 - Semiconductor Engineering today published a new article - Big Memory Shift Ahead - which looks at the cost, scaling and other technical pressures on legacy nand flash and DRAM which are the object of attack by other memory technologies.

"If these new memories really are as good as the claims, why are we not seeing them in production applications today?" - says Brian Bailey, Technology Editor - Semiconductor Engineering who wrote the article. "The answer appears to be inertia."

Dave Lazovsky, CEO of Intermolecular expands on this by suggesting - "NAND flash is a $30B industry that has tens of billions of dollars in capital infrastructure that would need to be retooled. The big 4 players represent 95% of the market and they have a lot of existing investment. The entire cost equation is CapEx, so they need to milk the tail of the revenues as long as they can." the article

Are you ready to rethink RAM?

Editor:- April 2, 2014 - We've all got used to the idea that a series of revolutions has been playing out in the enterprise server market centered around flash SSDs and - in that context - the developments in DRAM technology have sounded reassuringly boring and predictable.

But are you ready to rethink enterprise DRAM architecture too?

The state of blue sky thinking about enterprise DRAM - what is it really for? - and the changes that could lead to - are discussed in a new blog on the article

Samsung in volume production of 20nm DDR3 RAM

Editor:- March 11, 2014 - 40 years ago in the early days of MOS LSI - whenever semiconductor companies like Intel wanted to characterize a new semiconductor production process and establish the "safe" design rules for manufacturability at ever smaller chip geometries (aka "shrink") the circuit and product of choice for the fab architects was memory - even if the eventual product for the wafer fab was going to be a microprocessor.

More recently - in the past few years - if you've been looking at all those "nm" (nanometer) numbers in the news stories about IT related chips you can hardly fail to have noticed that it's been the flash memory devices which have been at the leading edge of the numbers. And when looking at production devices - flash has been about 2 years in advance of DRAM and server CPUs.

You've often heard on these pages that it's only by breaking the safe design rules used in preceding generations that interesting new SSDs come to market.

And a big part of the to-do list for any SSD controllers is to cope with a predictable scale and style of expected memory defects and virtualize them away - creating a usable base level storage device.

Fitting in line with this trend - Samsung today announced it's using 20nm technology in the production of new 4Gb DDR3 DRAM.

As comparison points:
  • Samsung was doing volume production of 10nm flash (used in consumer eMMC SSDs for mobile phones) in November 2012.
The way this pattern has been going in recent years is that the first volume uses of new silicon geometries go into consumer markets - where if there's a data upset - you can see something wrong happening (blue screen or freeze) turn the power off and try things again. After several quarters of doing this - the chip bakeries have finely tuned their recipes and are ready to guarantee a less crumbly dough mixture for use in the enterprise.

But if these concepts are new to you - it's not worthwhile memorizing them. Because 3D nand flash changes the priority of future enhancements towards a preference for building upwards in more layers instead of merely thinning sideways.

Virtium launches 32GB ULP RAM with industrial screening

Editor:- February 26, 2014 - Virtium today introduced 2 new low profile 16GB and 32GB DDR3 RAM modules in these form factors - ULP (Ultra-Low Profile) - 0.70" high and VLP (Very-Low Profile) - 0.738" high - for use in dense embedded servers which need industrial temperature operation in these form factors.

Editor's comments:- as with industrial SSDs - one of the differences in industrial memory is the screening process. Virtium's memory blog says that using 24 hour TDBI (Test During Burn-In) chambers can reduce early failures up to 90%.

See also:-
how bad parity lost Sun its reputation for SPARC reliability
general principles of improving electronic reliability by screening
An Empirical Study of Memory Hardware Errors in a Server Farm (pdf)

Hybrid Memory Cube gets x2 speedup

Editor:- February 25, 2014 - Although the market for Hybrid Memory Cube compatible RAM has barely begun - a new Gen2 specification was announced today which doubles the fastest short-reach data performance (previously 15Gb/s) upto 30Gb/s. See also:- ORGs, RAM DIMM compatible SSDs

the Top SSD Companies in Q4 2013

Editor:- January 31, 2014 - today published the 27th quarterly edition of the Top SSD Companies - based on market metrics in Q4 2013.

what changed in SSD year 2013?

Editor:- December 9, 2013 - The important ideas in the SSD market seem to change every year. To avoid making bad decisions you not only have to learn new SSD ideas but you also need to identify which old SSD ideas to forget. That's the theme of a new article on - what changed in SSD year 2013?.

Micron samples 2GB HMC

Editor:- September 25, 2013 - Micron today announced it's sampling the company's first implementation of the Hybrid Memory Cube (high density chip stacking architecture standard) which was launched in October 2011). Micron's SR (short reach) HMC provides 2GB DRAM in a BGA - with upto 160 GB/s bandwidth.

More smoke than fire at SK Hynix memory plant

Editor:- September 5, 2013 - Yesterday there was widely reported speculation about the possible market impact of a fire at an SK Hynix memory plant - which makes upto 15% of the world's DRAM chips.

In a clarification statement reported by Reuters the company said there was no material damaage to the clean rooms and SK Hynix anticipated that supply volumes would not be materially affected.

Editor's comments:- 3 weeks ago it was announced that 16nm flash from SK Hynix is the main memory building block in Skyera's 1U half petabyte skyEagle SSD rack.

DRAM technology won't advance soon - says Micron

Editor:- August 20, 2013 - In recent years the SSD market has become nearly 100% flash (and nv memory) focused - with little or no mention of DRAM based SSDs. The reason is that nearly every company whose product line used to be mainstream RAM SSD - has pulled out of that market or discontinued enhancements to those products. Flash SSDs are more economic and easier to sell.

It doesn't mean to say that the role of DRAM in SSD systems has entirely disappeared. It still appears as a cache or tier in many flash SSD arrays and the existence of some small percentage of DRAM is assumed in SSD caching software and also in (flash based) memory channel SSDs.

Micron sent out a useful signal of where its own DRAM roadmap is going in an article yesterday in EETimes - which reports an interview with Micron's president Mark Adams who said - "There will be no new greenfield DRAM fabs for the foreseeable future. We are hitting something of a lithography wall in DRAM where shrinks are getting tougher and gains are not as attractive, so people are not as financially motivated to invest in new fabs. Also we see planar DRAM advances will end in the next 3 to 5 years, so you probably cannot get ROI in a new planar fab." the article


Editor:- August 8, 2013 - SMART Storage Systems today announced it has begun sampling the first memory channel SSDs compatible with the interface and reference architecture created by Diablo Technologies.

SMART's first generation enterprise ULLtraDIMM SSD (ULL = ultra-low latency) can be deployed via any existing DIMM slot and provides 200GB or 400GB of enterprise class flash SSD memory with upto 1GB/s and 760MB/s of sustained read/write performance, with 5 microseconds write latency. Throughput, IOPS and memory capacity all scale with the number of ULLtraDIMM deployed in each server.

ultra low latency memory channel SSD

Editor's comments:- With the current design -only one DIMM slot in each server has to be reserved for conventional DRAM. Apart from that constraint any DIMM slot can be used for either flash or DRAM as deemed necessary for the application.

For more about the potential of this technology, the thinking behind it and the competitive landscape relative to PCIe SSDs etc see my earlier articles on the Memory Channel SSDs page.

Hybrid Memory Cube spec ready for chip designers

Editor:- April 3, 2013 - back in October 2011 - I reported on this page the formation of a new industry ORG - the Hybrid Memory Cube Consortium - which could have an impact on future SSD packaging densities.

It takes a while to get these things going - but according to a press release this week by one of the founding companies - Micron - the 100 plus companies which are collaborating in this enterprise have agreed on an interface specification (pdf).

A key feature of the new multiplane memory architecture is that distributed memory controllers in an HMC module will handle the data I/O packet requests for the bunch of stacked memory chips in its own vault. This is similar to the distributed intelligent data mover concept which is already used in all proprietary big architecture SSD controller designs - because it's the only way you can get good aggregated global system performance while also dealing with low level local memory management issues at low latency.

As with earlier generations of remote distributed memory interfaces - such as InfiniBand - HMC is designed to optimize the request of small packets - which in the case of HMC is 16 to 128 bytes of data.

With today's semiconductor speeds - accessing the data in those distributed memory chips within the same HMC module presents similar technical problems to distributed memory cards in traditional computer designs - because traversing inches of physical space at high speed is as difficult as moving data across tens of feet at slower speeds.

HMC has been born as a DRAM technology - but don't ignore it - just for that reason. (Or because the data packet sizes are small compared to the block sizes in nand flash.) If and when these HMC packaging ideas result in viable products - the ideas and methodologies will spill into SSDs too -regardless of what the underlying memories used in SSDs may be at that time.

It's all about speed and scalability. According to the HMC faqs page - A single (1st generation) HMC unit can provide more than 15x the bandwidth of a DDR3 module. See also:- SSD interface glue chips.

Micron sources power holdup technology for NVDIMMs

Editor:- November 14, 2012 - Micron has signed an agreement with AgigA Tech to collaborate to develop and offer nonvolatile DIMM (NVDIMM) products using AgigA's PowerGEM (sudden power loss controller and holdup modules).

NEC Hitachi Memory dream ends in Elpida bankruptcy

Editor:- February 27, 2012 - Elpida today announced it is reorganizing under the code of the bankruptcy laws in Japan.

Editor's comments:- The company's press release (pdf) relates a detailed history of problems starting in 2007 with the credit crunch, over capacity, falling RAM prices, increasing strength of Yen etc. The company - Japan's biggest surviving RAM maker - started out as NEC Hitachi Memory in 1999 and changed its name to Elpida in 2000.

Elpida never got into the SSD market. Now it looks like it never will.

A report in the New York Times says - "Elpida's bankruptcy filing is the biggest ever by a Japan-based manufacturer..."

Viking ships nv 8GB DDR3 DIMM

Editor:- October 18, 2011 - Viking Modular Solutions said it is shipping an extension of their nv module range.

The DDR3 ArxCis-NV plugs into standard RAM sockets and provides 2GB to 8GB RAM which is backed up to SLC flash in the event of a power failure - while the memory power is held up by an optional external 25F supercap pack. Viking says these new memory modules can eliminate the need for battery backup units in servers and the maintenance logistics associated with maintaining them. They are specified as being maintenance free for "5 years @ 60°C".

Editor's comments:- will these new modules replace batteries in RAM SSDs? - I doubt it - because of scalability issues - like managing a spiderweb of 100+ dangly bits of wire when you have a terabyte of RAM. Having said that - there are many applications which only use a small number of memory chips which could benefit from such a product.

Hybrid Memory Cube will enable Petabyte SSDs

Editor:- October 7, 2011 - Samsung and Micron this week launched an new industry initiative - the Hybrid Memory Cube Consortium - which will standardize a new module architecture for memory chips - enabling greater density, faster bandwidth and lower power.

"HMC is unlike anything currently on the radar," said Robert Feurle, Micron's VP for DRAM Marketing. "HMC brings a new level of capability to memory that provides exponential performance and efficiency gains that will redefine the future of memory."

Editor's comments:- HMC may enable SSD designers to pack 10x more RAM capacity into the same space with upto 15x the bandwidth, while using 1/3 the power due to its integrated power management plane.

The same technology will enable denser flash SSDs too - if flash is still around in 3 years' time and hasn't been sucked into the obsolete market slime pit by the lurking nv demons which have been shadowing flash for the past 10 years and been waiting for each "next generation" to stumble and be the last.

The power management architecture integrated in HMC and the density scaling it allows for packing memory chips (without heat build-up) are key technology enablers which were listed as some of the problems the SSD industry needed to solve in my 2010 article - this way to the Petabyte SSD.
"Across the whole enterprise - a single petabyte of SSD with new software could replace 10 to 50 petabytes of raw legacy HDD storage and still enable all the apps to run much faster while being hosted on a shrunken population of SSD enhanced servers."
meet Ken and the enterprise SSD software event horizon
Partial list of past and present RAM manufacturers - mentioned in storage news / history.

A-DATA, Adtec , AGIGA Tech , Alliance Semiconductor, ANACAPA, Apacer Memory America, ATP Electronics, Austin Semiconductor, Avant North America, Cambex , Century Microelectronics, Corsair Memory, Crucial Technology, Cypress Semiconductor, Dane-Elec Memory, Dataram, EDGE Tech, Elpida Memory, Fairchild Semiconductor, Gigaram, Hynix Semiconductor, IBM Microelectronics, Inotera Memories, Kentron Technologies, Kingston Technology, MemoryTen, Micro Memory, Micro Memory Bank, Micron Technology, Mosel Vitelic, Mushkin, MoSys, Nanya Technology, NEC, Netlist, Patriot Memory, Piiceon, PNY Technologies, Qimonda, Ramaxel Technology , Ramtron , Renesas Technology, Rocky Mountain Ram, Samsung Electronics, Silicon Mountain Memory, Silicon Power , SimpleTech, SMART Modular Technologies, Southland Micro Systems, Spansion, STMicroelectronics, Swissbit, TopRam, Toshiba, Transcend Information, TwinMOS Technologies, Unigen, Viking Modular Solutions, VisionTek, White Electronic Designs, Winbond Electronics , Z Tech International.
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"Among 129 DRAM modules we analyzed (comprising 972 DRAM chips), we discovered disturbance errors in 110 modules (836 chips). In particular, all modules manufactured in the past two years (2012 and 2013) were vulnerable, which implies that the appearance of disturbance errors in the field is a relatively recent phenomenon affecting more advanced generations of process technology. We show that it takes as few as 139K reads to a DRAM address (more generally, to a DRAM row) to induce a disturbance error."
Disturbance Errors in DRAM - an Experimental Study (pdf)

"Our past work showed that application-unaware design of memory controllers, and in particular memory scheduling algorithms, leads to uncontrolled interference of applications in the memory system." - said Onur Mutlu, Carnegie Mellon University.
Are you ready to rethink RAM?


re RAM - by Zsolt Kerekes, editor
RAM - Random Access Memory - is the fastest type of storage.

It's implemented by silicon chips which can contain upto thousands of millions of storage bits (gigabits) connected in a randomly accessible array.

The "random access" part of the RAM name was to differentiate RAM from earlier types of memory (more than 30 years ago) which were stored in blocks (or rings) which meant that reading or writing to selected memory bits involved processing the contents of the block through a shift register. RAM was easier to write software for and faster.

RAM has equal read and write access times (unlike flash memory). Other significant differences to flash are:-
  • the data stored in a RAM is only maintained while the device is powered up (is volatile)
  • RAM doesn't suffer from write wear-out (endurance)
  • RAM is typically more expensive than flash for the same capacity, and typically uses more electrical power. The exception is smaller capacity memories inside a chip where the complexity of managing flash memory incurs more overhead than the much simpler overheads in RAM.
RAM products have different designs and are optimized for various markets (such as servers, notebooks and graphics cache) based on their speed, cost, interface and capacity.

The earliest SSDs used battery backed RAMS. RAM SSDs still exist in 2011 and are economic in some high performance applications and sometimes use flash as the internal backup medium (instead of hard disks) to enable fast boot.

RAM is susceptible to random data corruption by radioactive particles which occur naturally in many locations - and which also strike the earth from cosmic rays. That's why ever since the earliest high density DRAM memory systems were designed in the 1970s - it has been necessary to integrate various types of error correction - ranging from simple parity checks, and error correcting codes right up to active data monitoring and healing in high capacity RAM SSDs which is implemented by dedicated RAM controllers.

image for ULLtraDIMM IBM article

"...The RAM market faces disruptive challenges from SSDs - just as hard disks have done. At some time during the next 5 years - most of the world's new memory will be deployed inside an SSD or an SSD controlled loop. Owning an SSD brand will be as important in the new market for memory makers as getting designed into tier 1 server slots was in the past. Commercial RAM makers will have to re-engineer themselves into SSD companies - or risk lower profit margins from selling to SSD brands at spot market prices from outside the SSD box."
...Editor:- talking to a market strategist in one of the world's biggest seminconductor companies in June 2011.

"I'm often asked if I could foresee how important (DRAM) would become," said Robert Dennard (the inventor of DRAM) on receiving a lifetime achievement award in 2005.

"I knew it was going to be a big thing, but I didn't know it would grow to have the wide impact that it has today." the article

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