|Samsung in volume
production of 3D DDR4 RDIMMs|
Editor:- August 27, 2014 - Although
the main interest in DDR4 RDIMMs - from an SSD market perspective - will be
in how that interface opportunity gets leveraged in
channel flash SSDs - let's not forget that the motherboard slots - which
will enable that market - have been designed for
DRAM. So the DRAMs will
come first and are an important part of the countdown to the new DDR4 flash DIMM
In that context I'd like to mention that Samsung is today
celebrating "a new milestone in the history of memory technology" with
the announcement that the company is in volume production of the industrys
first 64GB DDR4 RDIMMs
(DRAM) that use 3D through silicon via (TSV) stacked die package
technology and 20nm class die geometries.
Samsung says that the new
64GB TSV module performs 2x as fast as a 64GB module that uses
conventional wire bonding packaging, while consuming approximately 1/2 the
Editor's comments:- Samsung describes this announcement as "historic"
and I was content to include that positioning statement in the news above -
because much of what Samsung has done in the past has indeed had historic
For more examples - see "Samsung
historic" which gives you search results from the
Diablo unveils DDR-4 flash DIMM SSDs
7, 2014 - Diablo
yesterday announced details of a new 2nd generation
SSD - low latency flash SSD accelerators in DDR-4 sockets - which will
sample to oems in the first half of 2015.
Along with the new hardware
technology there will be an improved software platform - with features like
NanoCommit - which Diable says will enable hundreds of millions of
transactions per second, with nanosecond latency.
comments:- After FMS - Diablo sent me
more info (pdf)
about their FMS
presentation (pdf) from which I have extracted these key features.
- Diablo's converged memory architecture (flash tiered with DRAM) is planned
to support 700 million random cachelines / sec.
- Latency of each cacheline is about 48 nanoseconds.
- Diablo's NanoCommit supports byte addressable small writes to flash with
high transaction rates and the ability to mirror the DRAM contents to
- The combination of technologies would enable something like a 1U server
with 25TB of converged memory.
is there a market for I'M Intelligent Memory inside SSDs?
June 4, 2014 - Are there applications in the SSD market for DRAM chips which
integrate ECC correction inside the RAM chip - and which plug into standard
That was the question put to me this afternoon by Thorsten
Wronski - whose company MEMPHIS
Electronic AG distributes I'M Intelligent Memory in
Thorsten told me he's had a good reaction from the SSD
companies he's spoken to - which is why he phoned.
But in a long
conversation about the economics and architectures of end to end
in SSDs and the different
ratios of RAM cache
to flash in SSDs - I told him that my initial reaction was he should look
at embedded applications - which depend on the
reliability of a
single SSD - rather than enterprise systems in which the economics analysis for
arrays point to a system wide solution rather than a point product fix.
interesting thing is he said he's done tests on the new I'M memory as drop in
replacements for unprotected memory designs- in which he accelerated the likely
incidence of error events by increasing the interval between refreshes and
raising the temperature.
Here's what he said.
assembled a standard 1GB unbuffered DIMM with 8 chips of 1Gbit ECC DRAM. Then we
put this into a test board and ran RSTPro (a very strong memory test software).
No error found.
Next we put the whole board into a temperature chamber
at 95°C, which normally requires the refresh rate to be doubled (32mS
instead of 64mS). No error found.
Finally we wrote a software to change the refresh-register of the CPU
on the board, so we were able to set higher values. The highest possible was
750mS, so the DRAM did almost not get any more refreshes. Still it continued
working in RSTPro without a single error for 24 hours.
We tried the same with Samsung and Hynix modules, but none of them
came even close to those results. Most failed at refresh-rates of 150 to 200 mS,
which is not bad indeed. Many more tests will follow."
Editor's comments:- the reason I mention this - is because
adapting the refresh rate was one of the things mentioned in my recent blog -
Are you ready to
However - most of the leading SSDs in
don't have RAM caches for other reasons (to reduce the physical space, power
consumption, hold-up time, or because don't need the performance). So I told
Thorsten I don't see an industry wide demand inside SSDs. But some of you
might already have thought of applications.
I'M ECC DRAM product
big memory makers still need to recoup investments in flash and
DRAM before switching to newer technologies
Editor:- May 22, 2014 -
today published a new article -
Big Memory Shift
Ahead - which looks at the cost, scaling and other technical pressures on
legacy nand flash and DRAM which are the object of attack by other memory
"If these new memories really are as good as the
claims, why are we not seeing them in production applications today?" -
says Brian Bailey,
Technology Editor - Semiconductor
Engineering who wrote the article. "The answer appears to be inertia."
CEO of Intermolecular
expands on this by suggesting - "NAND flash is a $30B industry that has
tens of billions of dollars in capital infrastructure that would need to be
retooled. The big 4 players represent 95% of the market and they have a lot of
existing investment. The entire cost equation is CapEx, so they need to milk the
tail of the revenues as long as they can." ...read the article
Are you ready to rethink RAM?
Editor:- April 2, 2014
- We've all got used to the idea that a
revolutions has been playing out in the enterprise server market centered
around flash SSDs and - in that context - the developments in DRAM
technology have sounded reassuringly boring and predictable.
are you ready to
rethink enterprise DRAM architecture too?
The state of blue sky
thinking about enterprise DRAM - what is it really for? - and the changes
that could lead to - are discussed in a new blog on StorageSearch.com ...read the article
Samsung in volume production of 20nm DDR3 RAM
March 11, 2014 - 40 years ago in the
days of MOS LSI - whenever semiconductor companies like
Intel wanted to
characterize a new semiconductor production process and establish the "safe"
design rules for manufacturability at ever smaller chip geometries (aka "shrink")
the circuit and product of choice for the fab architects was memory - even if
the eventual product for the wafer fab was going to be a microprocessor.
recently - in the past few years - if you've been looking at all those "nm"
(nanometer) numbers in the news stories about IT related chips you can
hardly fail to have noticed that it's been the flash memory devices which have
been at the leading edge of the numbers. And when looking at production
devices - flash has been about 2 years in advance of DRAM and server CPUs.
often heard on these pages that it's only by
safe design rules used in preceding generations that interesting new SSDs
come to market.
And a big part of the to-do list for any
SSD controllers is to
cope with a predictable scale and style of expected memory defects and
virtualize them away - creating a usable base level storage device.
in line with this trend - Samsung today
it's using 20nm technology in the production of new 4Gb DDR3
way this pattern has been going in recent years is that the first volume uses
of new silicon geometries go into consumer markets - where if there's a data
upset - you can see something wrong happening (blue screen or freeze) turn the
power off and try things again. After several quarters of doing this - the chip
bakeries have finely tuned their recipes and are ready to guarantee a less
crumbly dough mixture for use in the enterprise.
- Samsung was doing volume production of 10nm flash (used in consumer
eMMC SSDs for mobile
phones) in November
But if these concepts
are new to you - it's not worthwhile memorizing them. Because
3D nand flash changes the
priority of future enhancements towards a preference for building upwards
in more layers instead of merely thinning sideways.
Virtium launches 32GB ULP RAM with industrial screening
February 26, 2014 - Virtium
new low profile 16GB and 32GB DDR3 RAM modules in these form factors -
ULP (Ultra-Low Profile) - 0.70" high and VLP (Very-Low Profile) - 0.738"
high - for use in dense embedded servers which need industrial temperature
operation in these form factors.
Editor's comments:- as with
- one of the differences in industrial memory is the screening process.
Virtium's memory blog
says that using 24 hour TDBI (Test During Burn-In) chambers can reduce early
failures up to 90%.
parity lost Sun its reputation for SPARC reliability
general principles of
improving electronic reliability by screening
Empirical Study of Memory Hardware Errors in a Server Farm (pdf)
Hybrid Memory Cube gets x2 speedup
25, 2014 - Although the market for Hybrid Memory Cube compatible
RAM has barely begun - a
new Gen2 specification was
today which doubles the fastest short-reach data performance (previously
15Gb/s) upto 30Gb/s. See also:-
the Top SSD Companies in Q4 2013
Editor:- January 31,
2014 - StorageSearch.com
today published the 27th
quarterly edition of the
Top SSD Companies -
based on market metrics in Q4 2013.
what changed in SSD year 2013?
Editor:- December 9,
2013 - The important ideas in the SSD market seem to change every year. To
avoid making bad decisions you not only have to learn new SSD ideas
but you also need to identify which old SSD ideas to forget. That's
the theme of a new article on StorageSearch.com
changed in SSD year 2013?.
Micron samples 2GB HMC
Editor:- September 25, 2013 -
it's sampling the company's first implementation of the
Hybrid Memory Cube (high
density chip stacking architecture
standard) which was
launched in October
(short reach) HMC provides 2GB DRAM in a BGA - with upto 160 GB/s
More smoke than fire at SK Hynix memory plant
September 5, 2013 - Yesterday there was widely reported speculation about
the possible market impact of a fire at an SK Hynix memory plant
- which makes upto 15% of the world's
statement reported by Reuters the company said there was no material
damaage to the clean rooms and SK Hynix anticipated that supply volumes
would not be materially affected.
Editor's comments:- 3 weeks
ago it was
that 16nm flash from SK Hynix is the main memory building block in
Skyera's 1U half
DRAM technology won't advance soon - says Micron
August 20, 2013 - In recent years the SSD market has become nearly 100%
flash (and nv memory)
focused - with little or no mention of
DRAM based SSDs. The
reason is that nearly every company whose product line used to be mainstream
RAM SSD - has pulled out of that market or discontinued enhancements to those
products. Flash SSDs are more economic and easier to sell.
mean to say that the role of DRAM in SSD systems has entirely disappeared. It
still appears as a cache
or tier in many flash SSD arrays and the existence of some small percentage
of DRAM is assumed in SSD
and also in (flash based)
sent out a useful signal of where its own DRAM roadmap is going in
article yesterday in EETimes - which reports an interview with
Micron's president Mark
Adams who said - "There will be no new greenfield DRAM fabs for the
foreseeable future. We are hitting something of a lithography wall in DRAM where
shrinks are getting tougher and gains are not as attractive, so people are not
as financially motivated to invest in new fabs. Also we see planar DRAM advances
will end in the next 3 to 5 years, so you probably cannot get ROI in a new
planar fab." ...read
SMART samples ULLtraDIMM SSDs
8, 2013 - SMART
Storage Systems today
it has begun sampling the first memory channel SSDs compatible with the
interface and reference architecture created by Diablo Technologies.
first generation enterprise
(ULL = ultra-low latency) can be deployed via any existing DIMM slot and
provides 200GB or 400GB of enterprise class flash SSD memory with upto 1GB/s and
760MB/s of sustained read/write performance, with 5 microseconds write latency.
Throughput, IOPS and memory capacity all scale with the number of ULLtraDIMM
deployed in each server.
comments:- With the current design -only one DIMM slot in each server has to
be reserved for conventional DRAM. Apart from that constraint any DIMM slot can
be used for either flash or DRAM as deemed necessary for the application.
more about the potential of this technology, the thinking behind it and the
competitive landscape relative to
PCIe SSDs etc see my
earlier articles on the
Hybrid Memory Cube spec ready for chip designers
April 3, 2013 - back in
October 2011 - I
reported on this page the formation of a new industry
ORG - the Hybrid Memory Cube Consortium
- which could have an impact on future SSD packaging densities.
takes a while to get these things going - but according to
press release this week by one of the founding companies - Micron - the 100 plus
companies which are collaborating in this enterprise have agreed on an
A key feature of the new multiplane memory
architecture is that distributed memory controllers in an HMC module will
handle the data I/O packet requests for the bunch of stacked memory chips in its
own vault. This is similar to the distributed intelligent data mover concept
which is already used in all proprietary
SSD controller designs - because it's the only way you can get good
aggregated global system performance while also dealing with low level
local memory management issues at low latency.
As with earlier
generations of remote distributed memory interfaces - such as
InfiniBand - HMC is
designed to optimize the request of small packets - which in the case of HMC is
16 to 128 bytes of data.
With today's semiconductor speeds -
accessing the data in those distributed memory chips within the same HMC module
presents similar technical problems to distributed memory cards in traditional
computer designs - because traversing inches of physical space at high speed is
as difficult as moving data across tens of feet at slower speeds.
has been born as a DRAM
technology - but don't ignore it - just for that reason. (Or because the data
packet sizes are small compared to the block sizes in
nand flash.) If and when
these HMC packaging ideas result in viable products - the ideas and
methodologies will spill into SSDs too -regardless of what the underlying
memories used in SSDs may be at that time.
It's all about speed and
scalability. According to the HMC
faqs page - A single (1st generation) HMC unit can provide more than 15x
the bandwidth of a DDR3 module. See also:-
SSD interface glue chips.
Micron sources power holdup technology for NVDIMMs
November 14, 2012 - Micron
has signed an
agreement with AgigA Tech to
collaborate to develop and offer nonvolatile DIMM (NVDIMM) products using
AgigA's PowerGEM (sudden power loss
controller and holdup modules).
NEC Hitachi Memory dream ends in Elpida bankruptcy
Editor:- February 27, 2012 - Elpida today announced
it is reorganizing under the code of the bankruptcy laws in Japan.
comments:- The company's
press release (pdf)
relates a detailed history of problems starting in 2007 with the credit
crunch, over capacity, falling RAM prices, increasing strength of Yen etc.
The company - Japan's biggest surviving RAM maker - started out as NEC Hitachi
Memory in 1999 and changed its name to Elpida in 2000.
Elpida never got
into the SSD market. Now it looks like it never will.
A report in the
New York Times says -
bankruptcy filing is the biggest ever by a Japan-based manufacturer..."
Viking ships nv 8GB DDR3 DIMM
Editor:- October 18,
Viking Modular Solutions
said it is shipping
extension of their nv module range.
ArxCis-NV plugs into standard
RAM sockets and provides
2GB to 8GB RAM which is backed up to SLC flash in the
event of a
power failure - while the memory power is held up by an optional external
25F supercap pack. Viking says these new memory modules can eliminate the need
for battery backup units in servers and the maintenance logistics associated
with maintaining them. They are specified as being maintenance free for "5
years @ 60°C".
Editor's comments:- will these new
modules replace batteries in
RAM SSDs? - I doubt it
- because of scalability issues - like managing a spiderweb of 100+ dangly
bits of wire when you have a terabyte of RAM. Having said that - there are many
applications which only use a small number of memory chips which could benefit
from such a product.
Hybrid Memory Cube will enable Petabyte SSDs
October 7, 2011 - Samsung
and Micron this
week launched an new industry initiative - the Hybrid Memory Cube Consortium
- which will standardize a new module architecture for memory chips -
enabling greater density, faster bandwidth and lower power.
is unlike anything currently on the radar," said Robert Feurle,
Micron's VP for DRAM Marketing. "HMC brings a new level of capability to
memory that provides exponential performance and efficiency gains that will
redefine the future of memory."
Editor's comments:- HMC
may enable SSD designers to pack 10x more
RAM capacity into the same
space with upto 15x the bandwidth, while using 1/3 the power due
to its integrated power management plane.
The same technology will
enable denser flash SSDs too - if flash is still around in 3 years' time and
hasn't been sucked into the obsolete market slime pit by the
lurking nv demons
which have been shadowing flash for the past 10 years and been waiting for each
"next generation" to stumble and be the last.
management architecture integrated in HMC and the density scaling it allows
for packing memory chips (without heat build-up) are key technology enablers
which were listed as some of the problems the SSD industry needed to solve
in my 2010 article -
this way to the
| "Across the whole
enterprise - a single petabyte of SSD with new software could replace 10 to
50 petabytes of raw legacy HDD storage and still enable all the apps to run
much faster while being hosted on a shrunken population of SSD enhanced
|meet Ken and the
enterprise SSD software event horizon|
|Partial list of past and present RAM
manufacturers - mentioned in
storage news /
AGIGA Tech ,
Apacer Memory America,
ATP Electronics, Austin Semiconductor,
Avant North America,
Micro Memory Bank,
Ramaxel Technology ,
Rocky Mountain Ram,
Memory, Silicon Power
Micro Systems, Spansion,
Viking Modular Solutions,
White Electronic Designs,
Winbond Electronics ,
Z Tech International.
||Despite the cost -
Megabyte found that
RAM gave him the fastest access to what he was seeking. |
| "Our past work
showed that application-unaware design of memory controllers, and in particular
memory scheduling algorithms, leads to uncontrolled interference of applications
in the memory system. |
"Such uncontrolled interference can lead to
denial of service to some applications, low system performance, and an inability
to satisfy performance requirements, which makes the system uncontrollable and
unpredictable" - said Onur Mutlu, Assistant Professor Electrical and
Computer Engineering - Carnegie Mellon University.
|Are you ready to
|re RAM - by Zsolt Kerekes,
|RAM - Random Access Memory
- is the fastest type of storage.|
It's implemented by silicon chips
which can contain upto thousands of millions of storage bits (gigabits)
connected in a randomly accessible array.
The "random access"
part of the RAM name was to differentiate RAM from earlier types of memory
(more than 30 years ago) which were stored in blocks (or rings) which meant that
reading or writing to selected memory bits involved processing the contents of
the block through a shift register. RAM was easier to write software for and
RAM has equal read and write access times (unlike
flash memory). Other
significant differences to flash are:-
- the data stored in a RAM is only maintained while the device is powered
up (is volatile)
- RAM doesn't suffer from write wear-out (endurance)
RAM products have different
designs and are optimized for various markets (such as servers, notebooks and
graphics cache) based on their speed, cost, interface and capacity.
- RAM is typically more expensive than flash for the same capacity, and
typically uses more electrical power. The exception is smaller capacity memories
inside a chip where the complexity of managing flash memory incurs more overhead
than the much simpler overheads in RAM.
earliest SSDs used battery backed RAMS.
RAM SSDs still exist in
2011 and are economic in some high performance applications and sometimes
use flash as the internal backup medium (instead of
hard disks) to enable
RAM is susceptible to random data corruption by radioactive
particles which occur naturally in many locations - and which also strike the
earth from cosmic rays. That's why ever since the earliest high density DRAM
memory systems were designed in the 1970s - it has been necessary to integrate
various types of error correction - ranging from simple parity checks, and error
correcting codes right up to active data monitoring and healing in high capacity
RAM SSDs which is implemented by dedicated RAM controllers.
|"...The RAM market faces
disruptive challenges from SSDs
- just as hard disks
have done. At some time during the next 5 years - most of the world's new
memory will be deployed inside an SSD or an SSD controlled loop. Owning an
SSD brand will be as important in the new market for memory makers as getting
designed into tier 1 server slots was in the past. Commercial RAM makers will
have to re-engineer themselves into SSD companies - or risk lower profit
margins from selling to SSD brands at spot market prices from outside the SSD
|...Editor:- talking to a market strategist in one
of the world's biggest seminconductor companies in June 2011.|
|"I'm often asked if I could foresee
how important (DRAM) would become," said Robert Dennard
(the inventor of DRAM) on receiving a lifetime achievement award in 2005.|
"I knew it was going to be a big thing, but I didn't know it would grow to
have the wide impact that it has today." ...read the