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XLC Disk

XLC Disk, Inc., founded in 2005 and based in Boulder, CO, is a fabless semiconductor company focused on the SSD market.

see also:- XLC Disk - editor mentions on STORAGEsearch.com

  • editor's comments:- March 2011 - XLC Disk (first mentioned on these pages 3 years ago - in March 2008) has been dipping in and out of stealth mode in recent years and does not yet ship any products or license any of its technologies.

    The company - which is well funded - is apparently developing advanced MLC technologies in preparation for an exploding SSD market which some SSD analysts believe could reach $100 billion / year in 2015.

    The company refuses to comment on when or what MLC level it will commercialize its products (x3 aka TLC, x4, x5?) - but the company's CTO, Dimitri Sholokov, has told me that unlike other flash SSD oems - who anticipate deep MLC SSDs going mainly into consumer markets - his company, XLC, is solving the technical problems needed to get data integrity, reliability and retention levels upto the standards needed for enterprise server apps.

    That's a starkly differenct philosophy to another stealth mode SSD company - Exabyte SSD - whose website is also currently blank. Exabyte SSD's view is that only SLC will be reliable enough for bulk storage SSDs - and their approach is to develop the architecture and technology for power management within such SSD controllers.
Unveiling XLC Flash SSD Technology - March 2008
editor's comments:- from my limited contacts with the founders of this company I expect XLC Disk's products to be flash SSDs - probably in 1.8" and 2.5" form factors.

Looking at their patent applications - it appears that XLC is a multi level cell flash technology which offers 4x the capacity of SLC and 2x the capacity of MLC for the same chip area.

It has been technically impossible for researchers in long established chipmakers like SanDisk or Samsung to commercialize reliable flash memory with more than 4 levels so I wondered - how is a well funded start-up like XLC going to do better than that?

XLC's founder refers to MLC as "dumb first generation multi level flash" and XLC as the "multi level flash of the future."

From what I can gather XLC's technology goes to the core of the multi level cell problem and the problems of logic level discrimination and data storage reliability.

Unless you're deeply versed in the internals of chip design - these notes won't help you. But it's very hard making reliable MLC flash - even when you control the whole process.

MLC flash chip companies get over the limitations by using extensive redundant data blocks and ECC. Until now no one has succeeded in storing more than 2 bits of data in a high density flash chip - and the reason lies in physics. When the stored charges are related back to voltage levels - there's a wide variation - not only over the whole area of the chip - but also in the same part of the chip over time - due to the accumulation (or changes) in charge in adjacent parts of the chip which may have occurred since the data was written.

In simple language - you don't always read out the same digital value that you wrote in. Because the variation and tolerances in the end to end read write process are greater than the thresholds between the logic levels.

The problem is mitigated in today's MLC SSDs - because there are only 4 levels to discriminate between. But when you try to increase this - to say 8 - then the unreliability of the read back data - is very high. Adding more ECC doesn't help - because you get into a situation where the unique data capacity (after ECC) is lower than that achieved with traditional MLC.

XLC's solution is design distributed discriminator circuits in zones throughout the chip - and instead of relying on just traditional ECC - they add redundant calibration cells in these zones which are prewritten with known data each time a block erase write cycle is done.

When a read cycle occurs - the converted voltage is compared - not to a fixed level or percentage of the rail - but to adjacent levels written by the calibration controller. Variations in charge and voltage in that zone of the chip affect djacent zones in a similar way. The discriminator circuits compare the address selected data cell with nearby calibrated cells. That means even if the voltage varies by 20% (which is more than the difference in logic levels) the loc state is read back correctly - because the read is effectively differential - the difference between adjacent known calibrated cells.

Although the internal read and write processes are slower than in SLC or MLC flash - the amount of data in a single cell can be much more. For example an 8 level XLC can store 3 bits of data in a single cell - which gives 2x the capacity of MLC and 4x as much as SLC. So from the external chip point of view the data throughput is similar (or more) than SLC even though the internal chip latency is slower. One by product of the process is better endurance than MLC - approximately 2-3 times better (but still much lower than SLC).

XLC won't say yet how many levels for XLC the first commercial devices will have. They are characterizing the technology across a range of foundry technologies. And that's another difference. XLC is less process dependent than MLC.

XLC holds the promise of shattering the cost per gigabyte gap which has separated flash SSDs from hard disk drives. I look forward to the first unveiling of this technology, here on STORAGEsearch.com April 1, 2008.
  • ...Later:- the first draft of the article above (written in March 2008) was meant to be a work of fiction - and a spoof April 1st news story. Although I had the sneaking feeling that some of the ways I had "invented" of solving the multi level data problem might work at some time in the future...

    To add authenticity to the spoof - I contacted Jim Handy at Objective Analysis to elicit an analyst's comment on the new technology.

    You can imagine my delight when he said SanDisk was already working on something which sounded very similar. That shows that the SSD industry is programmed on a "fast forward" rate that can surprise us all - even editors who are embedded in the market.
other references to 3 / 4 bit MLC flash

An article by Lane Mason (Denali Software, Inc) looks forward to "...an 8-12x price reduction, in solid state storage, by the move to 4-bit MLC cells, by 2012,"

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"And here's a weird thing about acronyms. TLC can mean "triple level cell" flash - aka "x3". But it can also mean "tender loving care". And SSD IP is where the 2 TLCs can gainfully conjoin..."
...from:- MLC flash lives longer in my SSD care program - May 17, 2012
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DensBits samples new TLC flash controller
Editor:- April 30, 2012 - DensBits today released a new SSD controller - the DB3610 - which supports the latest 2Xnm and 1Xnm TLC (3 bits/cell ) MLC flash with an extreme endurance figure of more than 10K P/E cycles and R/W performance of up to 95MB/s / 65MB/s and 4,000 / 1,100 R/W IOPS (4KB), for sequential and random operations, respectively.

DB3610 employs DensBits' Memory Modem technology (adaptive DSP in SSD IP) which enables a native TLC solution with more than double the endurance of 2 bits/cell (MLC), and near-MLC R/W performance.

Editor's comments:- It's easy to miss the significance of new SSD products and technologies. And you might think from looking at the text and numbers above - this is a consumer style SSD controller - and it's not for me.

But I think DensBits may become one of the top 20 SSD companies real soon - unless it gets acquired before that happens.
SSD symmetries article ... Its flash technology has very high roadmap symmetry and the potential to impact competitiveness in the consumer, embedded and fast-enough enterprise SSD markets with a splash that's as big as SandForce made when it emerged on the scene 3 years ago.
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Bad block management in flash SSDs
This is an introduction to the thinking behind one of the many vital functions inside a flash SSD controller.

Native media defect quality in new flash memory chips has grown steadily worse in the past 10 years as geometries have shrunk.
click image to read the article - principles of bad block management in flash SSDs This article enumerates the scale of the problem and explains how intrinsically dodgy flash memory is transformed into dependable flash SSDs which you can entrust with your data. ...read the article
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Data Integrity Challenges in flash SSD Design
Editor:- Data Integrity Challenges in flash SSD Design is an article - written by Kent Smith Senior Director, Product Marketing, SandForce.

Reliability is the next new thing for SSD designers and users to start worrying about.
read the article about SSD integrity A common theme you will hear from all fast SSD companies is that the faster you make an SSD go - the more effort you have to put into understanding and engineering data integrity to eliminate the risk of "silent errors." ...read the article
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SSD Data Recovery Concepts
It's hard enough understanding the design of any single SSD. And there are so many different designs in the market.

Have you ever wondered what it looks like at the other end of the SSD supply chain - when a user has a damaged SSD which contains priceless data with no usable backup?
broken barrel image - click to read this data recovery article If so - this article - written by Jeremy Brock, President, A+ Perfect Computers - who is one of a rare new breed of SSD recovery experts will give you some idea. read the article