sudden power loss
are we ready for
infinitely faster RAM?
| hold up
capacitors in 2.5" MIL SSDs|
do you really need them?
Editor:- I've been looking at different aspects
of power hold up schemes in mission critical non volatile memory systems for
over 30 years. |
But every time I revisit this vast topic and compare
fresh examples from the market - I learn something a little bit new.
to three seconds - demonstrates the extreme range of hold up times
now in the market inside leading edge 2.5" military flash SSDs.
|flash wars in the
enterprise - MLC brand X|
|First you learned about SLC (good flash).
Then you learned about MLC (naughty flash when it played in
the enterprise - but good enough for the short attention span of consumers).
Then MLC SSDs learned how to be good.
Now some MLC is much nicer than others. - When it's preceded by an "e"
(extra-good). But it costs more.
But other people say you don't need
the expensive "e" - because their controllers empathize better
with naughty flash. (They really care about naughty flash being sent to bad
block jail too soon.)
Is your head ready to explode yet?
It's going to get even more complicated.
sugaring MLC for
|How big was the
thinking in this SSD's design?|
|Does size really does matter in SSD
By that I mean how big was the mental map? - not how many
inches wide is the SSD.
The novel and the short story both have their
place in literature and the pages look exactly the same. But you know from
experience which works best in different situations and why.
it comes to SSDs - Big versus Small SSD architecture - is something which was
in the designer's mind. Even if they didn't think about it that way at the time.
||For designers, integrators,
end users and investors alike - understanding what follows from these simple
choices predicts a lot of important consequences. ...read the article|
|3 things that could have
killed flash SSDs|
emerging size of
the flash SSD market as you see it today was by no means inevitable. It owes a
lot to 3 competing storage media competitors which failed to evolve fast enough
in the Darwinian jungle of the storage market in the
One of these 3 contenders is definitely on the road to extinction -
but could one of the other 2 still emerge to threaten flash SSDs?
SSD's past phantom
demons explores the latent market threats which hovered around the flash SSD
market in the past decade. They seemed real and solid enough at the time.
|| Getting a realistic
perspective of flash SSD's past demons (which seemed very threatening at the
time) may help you better judge the so-called "new" generation of nv
memory contenders - which are also discussed in the article. ...read the article|
|this way to the Petabyte
|In 2016 there will be
just 3 types of
SSD in the datacenter.|
of them doesn't exist yet - the bulk storage SSD.
It will replace the
last remaining strongholds of
hard drives in the
datacenter due to its unique combination of characteristics, low running costs
and operational advantages.
||The new model of the
datacenter - how we get from here to there - and the technical problems which
will need to be solved - are just some of the ideas explored in this
storage glue chips and IP sauce - news
|Marvell samples first
NVMe-oF SSD Converter Controller|
Editor:- August 7, 2018 - Marvell today
it is sampling a new controller to simplify the design of Ethernet connected
The 88SN2400 - which is aimed at a EBOF (Ethernet
Bunch of Flash) applications - utilizes a simple, low-power and compute-less
Ethernet fabric instead of a
fabric controlled and managed by an enterprise-class server SoC with integrated
As an indicator of performance Marvell says that a
typical 2U24 shelf with populated with 88SN2400 attached SSDs can support up
to 18M IOPS. Utilizing a Marvell Ethernet switch that supports 2Tb/s and the
Marvell 88SN2400, data center operators will be able to benefit from a 150GB/s
pipe of pooled storage, and better power consumption per IO compared to general
purpose architectures. The SSD converter controller is optimized for a small
footprint and can be attached to existing backplanes providing ease of service
and eliminating single point of failure. The technology can also be designed
into future Marvell SSD and emerging SCM controllers.
Micron hints at AI assisted porting of compute intensive
models to FPGA-inside memory array accelerators
Editor:- March 30,
2018 - A new blog -
Memory Matters in Machine Learning for IoT - by Brad Spiers - Principal
Solutions Architect, Advanced Storage at Micron reveals
significant progress in software tools development which is intended to reduce
the time and complexity of porting machine learning models onto in-situ memory
accelerators implemented by FPGAs embedded into DRAM arrays. The blog makes
specific reference to applications with Micron's PCIe connected
Computing Solutions (pdf) - which provide FGAs integrated with either DDR-3
or HMC and a design, simulation and runtime support tools.
things - Brad Spiers says... "Micron is engaged with machine learning
experts, like FWDNXT, to enable seamless transfer of machine learning models
onto FPGAs. Models are first created in the normal way, using the same software
that data scientists use every dayCaffe, PyTorch or Tensorflow. The
models output by these frameworks are then compiled onto FPGAs by FWDNXT's
Snowflake compiler." ...read
Editor's comments:- creating AI based software
productivity tools which could cut many months off the design time to create
FPGA based in-situ memory based application accelerators is an extreme case of
Defined Software. Such developments could become as significant for
startups creating blue sky HPC based knowledge enabling tools as was the
availability of microprocessor development systems for the democratization of
digital electronics in the 1970s.
IntelliProp demonstrates Gen-Z memory controller
November 13, 2017 - IntelliProp
its was demonstrating a memory controller for the emerging Gen-Z memory
IntelliProp's Gen-Z IPA-PM185-CT "COBRA"
controller combines DRAM and NAND and sits on the Gen-Z fabric, not the memory
bus. COBRA has the ability to support byte addressability to DRAM cache and
Block addressability to NAND flash. COBRA-based Gen-Z memory modules provide low
latency, persistent, shared memory access to multiple processors and
accelerators on the Gen-Z fabric supporting up to 32GB of DRAM and 3TB of NAND.
Embedded NVM - à la mode in September
July 28, 2017 - The South of France isn't a location which would have sprung to
my mind as the most obvious place to look for an event related to non volatile
memories and embedded designs. But in that respect I was wrong. The Leading Edge Embedded NVM Workshop will
take place September 25 to 27, 2017, in Gardanne (Aix en Provence area,
day program of presentations (pdf) includes speakers from around the world.
Here are some of the titles of the papers to give you an idea of the spread
- "Inkjet - Printed Flexible Conductive Bridge RAM"
- "Secure Characterisation of the OxRAM Technology."
- "Voltage Compatibility of ReRAM operation with CMOS"
- "Scaling and Demonstration of a 28nm Logic-Process-Compatible
Split-Gate Flash Memory Technology"
the value of 5 microseconds latency for Excelero
May 24, 2017 - 10 microseconds is the latency advantage of Excelero's
proprietary NVMesh compared to simple NVMeoF when managing fabrics of
dispersed NVMe SSDs in a PCIe connected network. More details like this appear
in a new blog on InfoWorld -
storage architecture for the enterprise - by Yaniv Romem CTO and
Tom Leyden VP of
corporate marketing at Excelero. ...read
Editor's comments:- when Excelero emerged from
stealth in March
2017 the low latency overhead of their software was a big deal - at just 5µS
compared to accessing a similar SSD in the same rack.
This is an
industry magic ballpark number which has been quoted as a worst case response
in earlier years by several pioneers in big memory architectures - including
details may have changed or been refined since.)
SCM DIMM wars
watchers know that if you can get inside that curve for most of your worst case
latencies then (with enough memory and cache) you can run popular memory
hogging applications with better performance than using traditional DRAM in
traditionally networked servers. PCIe fabrics compete and collaborate in the
memory systems market. Latency lessons learned from one of these contexts
can be used to guide initial expectations (subject to verification) in the
IP-Maker elevates performance ceiling of low power embedded
systems with "no server CPU" NVMe SSD FPGA IP
April 19, 2017 - A dilemma for designers of embedded systems which require high
SSD performance is how can you get the benefits of enterprise class NVMe SSDs
for simple applications - which integrate video for example - without at the
same time escalating the wattage footprint of the entire attached micro server?
new paper published today by IP-Maker -
server-class storage in embedded applications (pdf) discusses the problem
and how their new FPGA based IP enables any NVMe PCIe SSD to be used in
embedded systems to provide sub-microsecond latency using "20x better power
efficiency, and 20x lower cost compared to a CPU-based system."
company says the NVMe host IP - which is now available - can be used in an FPGA
connected between the PCIe root port and the cache memory, internal SRAM or
external DRAM. It fully controls the NVMe protocol by setting and managing the
NVMe commands. No CPU is required. It supports PCIe gen 3 x 8 interface.
Michael Guyard, Marketing
Director said that - among other things - applications include:-
- military recorders
- portable medical imaging
- mobile vision products - in robots and drones
Editor's comments:- Now Cinderella
embedded systems with low cost budgets and low wattage footprints can go to the
enterprise NVMe performance ball. The new magic - in the form of the FPGA IP
released today by IP Maker - has the potential to change the demographics of
the class of SSDs seen in future industrial systems.
a new name in SSD fabric software
Editor:- March 8,
2017 - A new
SSD software company
- Excelero -
has emerged from stealth today.
Excelero which describes itself as
- "a disruptor in software-defined block storage"
version 1.1 of its NVMesh® Server SAN software "for exceptional Flash
performance for web and enterprise applications at any scale."
company was funded in part by Fusion-io's founder
Editor's comments:- An easy way to understand what this kind
of software can do for you is to see how Excelero created a petabyte-scale
shared NVMe pool for exploratory computing for an early customer - NASA/Ames.
The mitigation of latency and bandwidth penalties enabled by the new
environment enabled "compute nodes to access data anywhere within a data
set without worrying about locality" and helped to change the way that
researchers could interact with the data sets which previously had been
constrained in many small islands of low latency. ...read
the white paper (pdf).
A3CUBE and memory fabrics....
Editor:- January 10,
2017 - When A3CUBE
started talking about supporting big memory fabrics with PCIe (in
there weren't too many
choices out there.
Now in 2017 the
SSD and SCM news pages are
awash with announcements about big memory systems. And growing industry support
for NVMe over Fabric was one of the big market developments in
already seeing signs of clear fragmentation in the memory fabric market
(mostly via server based interface expansion preferences such as
GbE but some of the memory
applications are also being cannibalized by tiered memory, new semiconductor
memory solutions and DIMM wars.)
this context it was interesting to see a recent
video (January 2017)
from A3CUBE which shows how their PCIe connected shared memory fabric can work
with NVMe components too. ...see the video
Mobiveil's Universal NOR Controller Allows SoC Designers to
Leverage Adesto's EcoXiP Flash Memory
Editor:- November 30, 2016
- Mobiveil today
it is working with Adesto Technologies
to enhance the memory in low capacity intelligent IoT systems.
Incorporating Mobiveil's U-NFC controller to control the new Adesto
EcoXiP flash will
provide SoC designers an eXecute-in-Place solution that more than doubles the
performance of alternative approaches using standalone NOR-Flash memory.
Rambus and Xilinx partner on FPGA in DRAM array technology
October 4, 2016 - Rambus
a license agreement with Xilinx
that covers Rambus' patented memory controller, SerDes and security
Rambus is also exploring the use of Xilinx FPGAs in its
Data Acceleration research program. The SDA - powered by an FPGA paired
with 24 DIMMS - offers high DRAM memory densities and has potential uses as a
CPU offload agent (in-situ
IDT discloses design win in Diablo's Memory1
September 27, 2016 - IDT
that Diablo Technologies
has selected IDT's
LRDIMM chipset as the preferred interface solution for its Memory1 128GB
system memory module.
"(Our) chipset is an essential enabler of
cutting-edge NVDIMM applications, such as Memory1," said Sean Fan, VP and GM
of IDT's Computing and Communications Division. "Such solutions have the
potential to change the entire landscape of in-memory computing, and it's an
exciting place for us to demonstrate our industry leadership."
also:- what's RAM really?
- RAM in an SSD context
eMemory Receives TSMC IP Partner Award
September 23, 2016 - eMemory
that over 260 of its silicon IPs have been deployed on TSMC's Open Innovation
new memories? new security risks?
Editor:- August 4,
2016 - Is remanence a security risk in persistent memory? That's the topic of
my new blog
you aren't yet ready to evaluate these new SCM style NVDIMMs you might think
you can skip this article.
That's OK as long as you already were aware
that that data recovery
has always been feasible in old style
DRAM too. ...read the
new paper discusses how to deploy same core DRAM controller IP
across diverse markets to increase reliability without prejudice to cost
July 30, 2016 - in a new paper -
of a Segment-Specific DDRn Memory Controller and PHY IP Solution (pdf)
which looks at the thinking behind a new DRAM controller IP by Cadence (which is
designed to satisfy many different markets) - the author, Eric Esteve, founder of
IP-nest, notes that it is
desirable to support different clock speeds for different markets and this
will require trade-offs in data integrity.
The dilemmas of how to
satisfy the cost budgets of diverse markets with low chip footprints while
offering the promise that higher volumes will result in better reliability for
all the SoCs which use the same DRAM controller IP are explored in this paper.
other things Eric says - It may look strange to see a higher data rate for
mobile than for infrastructure
until you realize that the end user expects
to benefit from good entertainment experience, and is not necessarily linked
with the maximum possible data integrity. When watching a video, this high data
rate guarantees good image quality, but when/if a wrong pixel (due to one data
bit in error) is inserted in the movie or video, it doesn't impact the user
This is the same argument which was used
historically to justify worse
in consumer SSDs
(compared to enterprise SSDs) although nowadays the cushioning impact of
software enables a
greater degree of freedom for
Seeing the feature specific trade-offs at the DRAM
controller IP level being discussed makes for interesting reading. ...read
the article (pdf)
SST qualifies NOR SuperFlash on mixed signal platform
July 12, 2016 - SST
qualification and availability of its low-mask-count embedded
NVM on GLOBALFOUNDRIES' 130 nm
advanced analog, mixed-signal and RF technology platform.
embedded SuperFlash memory solution requires the addition of only 4 masking
steps to enable cost-effective, high-endurance embedded flash for demanding
battery-powered applications such as drones, intelligent motor control, and
normally-off mobile computing.
Altera paper - FPGA offload in cohabiting memory arrays
June 8, 2016 - a recent white paper from Altera -
10 MX Devices Solve the Memory Bandwidth Challenge (pdf) - discusses the
role of more intelligent FPGA usage in next generation DRAM architecture.
the design challenges from power budgets and bandwidth constraints on chip pins
from legacy logic and memory approaches - Altera says its memory
cohabiting FPGA architecture -
unlocks new applications.
"One of the key functions for FPGA
offload involves data extraction and comparison with in-memory data structures.
For these access patterns, the increased bandwidth, channel count (from 4
interfaces to 64 channels), and increased open bank count (from 64 banks to 512
banks) have positive impacts on memory subsystem performance. The extra channel
count and bank pool count allows more accesses to hit successfully on open DRAM
banks. Because operations can avoid the bank activation penalty, this
implementation increases performance." ...
read the article (pdf)
what do today's prototype kits tell us about IoT's future?
May 9, 2016 - An interesting preview of raw technology ingredients in the
future IoT mix is -
DIY Development Boards for IoT Prototyping written by Janakiram MSV, Founder
Janakiram & Associates - published
in the New Stack.
includes prices and capabilities for a range of prototyping boards. ...read
data wipe-out video
Editor:- April 29, 2016 - Usually the last
thing you want to see as an SSD designer is your hot new product going up in
smoke - but autonomous self destruct of SSD data takes many forms and this is
one of them.
from Renice Technology
shows a verification test rig for this functionality. Renice says it
uses a specially designed electric circuit, which ensures that all NAND flash
chips in the SSD will be burned through. ...watch
Editor's comments:- I've asked Renice if they've analyzed the
composition of the smoke - but this kind of
fast purge is aimed
applications rather than civilian offices - so smoke fumes are the lesser of
two evils (compared to data capture by a foe).
PCIe 4.0 Multi-Lane PHY milestone
14, 2016 - Signs of onwards and upwards progress towards future
PCIe SSD speeds
emerged today in an
have demonstrated electrical interoperability for PCIe 4.0 with "robust
signal integrity" (BER below 10-15) at 16Gbps with 4 lanes running
new blog looks at DRAM latency creep
3, 2016 - We've got used to the fact the performance and characteristics of
fast flash SSDs
owe more to the interface, controller
design and software
than to the intrinsic timing and reliability of a
nand cell. But what about
DRAM? Isn't that much
closer to the raw, organic memory ingredients?
In a new blog on
indeterminate latencies and the virtual memory slider mix - I look at the
growing gap between server memory performance and the capabilities of raw,
organic DRAM cells.
As enterprise RAM performance is progressively
bounded more by controller traffic analysis needs and power consumption rather
than DRAM cell capability - there's an argument for saying if the statistical
distribution of DRAM latencies is so wide - maybe no one would notice if you
slipped in a different kind of memory in the virtual slider mix.
that - of course - was precisely the open barn door - which ushered in the
explosion of DRAM lookalike alt nvm announcements in
2015. ...read the new
memory tiers for datacenters and ultra high endurance flash for
automotive market to be discussed at ISSCC
editor:- January 14,
2016 - ISSCC (International Solid-State
Circuits Conference) will start January 31 (in San Francisco,
cost $1,030 or less
for IEEE members) so I looked at their
(pdf) to see papers relevant to SSDs. Among others things:-
- Basics of Memory Tiers in Compute Systems and a server TCO model - by
Technical Lead - Platforms Advanced Technology Team - Google
- Rethinking Memory Architecture - by Dean Klein VP
Memory System Development - Micron
- 256Gb 3b/Cell V-NAND Flash Memory with 48 Stacked WL Layers by a team from
- A 90nm Embedded 1T-MONOS Flash Macro for Automotive Applications with
0.07mJ/8kB Rewrite Energy and Endurance over 100 million cycles by a team from
IDT samples power management chip for enterprise SSDs
November 19, 2015 -
it is sampling a new multi-channel power management IC (PMIC) optimized for
($5.20 each, 1,000 unit price point ) is a flexible, programmable PMIC which
can shorten time to market by enabling the reuse of power management subsystems
across multiple protocols - SAS, SATA and PCIe - and form factors. Its design
delivers an effective power backup system that's been proven in the field, as
well as stability proven in earlier generation SSD products.
2.5 to 3D architectures point the way to DDR4's successor says
new blog on SemiWiki.com
Editor:- July 12, 2015 - "DDR4 will
be the last version of the DDR interface route for RAM, don't ever expect to see
DDR5" - says Eric Esteve
in his blog -
High Bandwidth Memory to Select after DDR4? - on SemiWiki.com - in which - as part of
getting us to contemplate the big architecture picture - he also says - "DDR4
is not only the last DDR, it's also the last protocol based on 2D (layers)
the article, SSD glue chips,
RAM in an SSD context
IP-Maker's NVMe IP passes UNH-IOL's compatibility
May 22, 2015 - IP-Maker
- which is represented in the US by Fides
Sales - today announced that its
data transfer manager design has passed the
UNH-IOL compatibility tests and is now
listed on their NVMe
compatibility integrator's list.
IP-Maker's IP supports
performance in the range of 350K IOPS and 10µs latency in a Gen2 x4
"We are pleased to announce this important
milestone", said Mickael
Guyard, co-founder of IP-Maker. "We are now able to provide a
compliant and high performance NVMe solution, helping storage companies to
develop PCIe SSD in a
reduced design time."
Northwest Logic has FPGA support for Everspin's MRAM
February 9, 2015 - Northwest
controller support for Everspin's
ST-MRAM - with interoperability proven on a Xilinx Virtex-7 FPGA platform.
MRAM's core IP also supports traditional volatile DDR3 SDRAM - so the
new support for MRAM will simplifiy the design of
protected low latency
Mobiveil supports Spansion's HyperBus NOR
Editor:- February 3, 2015
it will provide authorized controller support for Spansion's
flash chips are low capacity, low pin count, faster (5x) NOR flash (BGAs)
suited for some applications in the automotive electronics market.
HyperBus flash interface
IP (pdf) delivers upto 333MB/s using this 12-pin interface.
Microsem licenses DPA countermeasures from Rambus
January 29, 2015 -
will serve as reseller in the government and military sectors for certain
differential power analysis (DPA) technologies developed by Rambus's
cryptography research division.
As the first major FPGA company to
countermeasures, Microsemi has identified DPA as a significant vulnerability
in chip security, specifically for the mission-critical applications found in
government and military
GUC announces new low power SSD IP portfolio
September 25, 2014 - Global Unichip
out an expanded interconnect low power IP portfolio for ASICs targeting SSD
The expansion covers ultra low power PCIe 3/4 PHY,
DDR3/4, LPDDR3/4 CTRL/PHY and ONFi4.0 IO/PHY. IP based on the 28HPM/HPC
processes in the expanded portfolio are available now, while 16nm macros will be
available in Q4 of this year.
Among all NAND applications Global
Unichip says SSD is the fastest growing with the Data Center and Enterprise
segments showing the greatest potential. GUC is meeting that demand with a
complete low power IP portfolio for SSD controllers, including NAND I/O (ONFI,
Toggle), DDR I/F (DDR3/4, LPDDR3/4) and Serdes I/F (PCIe-3/4, SATA3/SAS3).
is it time for the SSD market to reconsider RapidIO?
May 14, 2014 - You'd think that with all the interfaces
already in use
within the enterprise SSD
market - there wouldn't be enough of a market gap to justify introducing
yet another one. - Particularly when that interface strays across low
latency server-storage territory which is dominated by
PCIe SSDs, under
attack by memory
channel SSDs and has been flanked historically by
thought so too.
But a recent article -
You Really Know RapidIO? - by Eric Esteve , founder of
IPnest says - "Maybe it's
time for the server/storage industry to give a second chance for the RapidIO
Editor's comments:- That's a bold statement -
coming as it does from someone who was involved in designing one of the first
generation PCIe controllers 10 years ago. Eric argues that the intrinsic fabric
architecture and routing support in RapidIO - would make many of the things
which architects are trying to do today - such as interconnecting large numbers
of servers and SSDs for example - easier and faster.
PCIe and Ethernet as sub microsecond CPU interconnects - view from
|Megabyte 's SSD glue was a
sticky paste of Phy IP, |
FPGA and ASIC granular chips stirred in a
trapping dielectric suspension and topped with a
quick setting, sweet tasting, firmware emulsifier.
|"While NVMe over PCIe
shaves off about 10us relative to SAS, NVMf can shave off about 100us from the
roundtrip latency between two hosts relative to protocols such as iSCSI. It also
saves CPU usage from TCP/IP processing. |
This can be particularly
beneficial in scale-out systems for transferring data between hosts. It does
require RDMA-capable NICs and DCB-capable switches, so it will take some time
for mass adoption."
founder and CTO, Nimble
Storage in his blog -
and NVMs - What to Expect (December 28, 2016).|
|Advanced decoding schemes
employing soft decoding use the NAND statistics and soft information to
determine the most probable read signal that corresponds to the actual stored
data. This allows you to obtain readable data even when the memory cell is
severely degraded or there is a lot of 'noise' in cell data. |
|Adaptive R/W &
DSP ECC in flash SSDs|