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the unsung hero of 3D endurance
Editor:- September 15, 2015 - One of the interesting surprises about 3D nand flash which emerged early in 2014 was that the endurance - reported by SSD designers - was better than you would have expected if you had taken as your starting point - assumptions about 2D nand with similar capacity and next generation (smaller) planar geometries.

Part of the explanation - which I discussed last year - was the use of different materials.

But there's more to it than that as I realized today in a new (to me) white paper The V-Nand paradigm shift (pdf) mentioned in an email blast from Samsung.

In Samsung's version of 3D - the charge is held in a silicon nitride charge trap - which has better insulating properties than conventional 2D materials - and lower leakage. (Essential if you think about it to even get a hope of doing more levels.) That's the bit I already wrote about.

What I didn't appreciate before was this.

The SiN charge trap requires a lower voltage to program each cell than traditional 2D (floating gate) designs. (The destructive effect of the energy in these write pulses is one of the contributory factors to cell wear in 2D.)

The combination of better insulation and less destructive write process would give you a better endurance figure for the same flash process geometry in nanometers.

But a 3rd element in Samsung's 32 layer 3D (which you could say is the sneaky pragmatic business decision bit) is that these devices weren't 2Xnm geomtery at all.

Samsung decided to bring this technology to market with a mature proven 3Xnm process. (3Xnm gives you better endurance anyway than 2Xnm in 2D flash.)

So when Samsung talk about their 32 layer V-nand - with 35,000 P/E cycles "offering 10x increase in endurance over the 3,000 cycles provided by planar (2D) NAND" there are several ingredients which combine to get this headline figure. And that's why this paper is useful.

As to how much of that "10x" will continue to be sustainable as more layers are added and as cell sizes get smaller - will remain to be seen. Samsung's paper suggests that they are hopeful about aiming at 100 layers in the next few years.

But it's clear that a lower write pulse voltage is one of the unsung heroes in this better endurance story. ...read the white paper

PS - not everyone is convinced about the market transforming imminence of Samsung's 3D nand.

In his August 2015 paper - Flash Technology:Annual Update (pdf) - Jim Handy founder Objective Analysis said "Samsung is shipping at a loss and we have found no evidence of a data sheet." Furthermore Jim is sceptical about the 3D nand industry's assertions that " the big ramp will be in 2017."
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NV + 0.4 DWPD @ 85C = V
0.4 DWPD at 85 degrees C for 5 years is enough to destroy the non volatility of MLC flash.

The raw data and comparisons with other temperatures can be seen in the blog - temperature considerations in SSDs (pdf) - by Virtium - which designs SSDs for the industrial market.
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The first time I saw the term "Garbage Collection" in an SSD context on StorageSearch.com was in 2002.

It was in an article about flash SSD reliability.
flash SSD Jargon Explained
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Even if you already knew that adaptive R/W and DSP ECC was an essential way for getting usable SSDs out of smaller 2D nand flash - then there are even more reasons for using this technology on the journey in 3D.

Among other things DensBits says that the scope for inter-cell interference grows from 8 identifiable routes in 2D to 26 for each cell in 3D.
Adaptive flash care management & DSP IP in SSDs
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what's the SSD market readiness of ReRAM and alternatives to nand flash?
news about nand flash memory
and other SSDward leaning nvms too
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SSDs are only as good as the people who design them and make them.

There can be orders of magnitude difference in operational outcomes - even when different SSD makers are using exactly the same memory chips.
principles of bad block management in flash SSDs