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| As every SSDmouse knows -
measuring stuff and adapting to what you know gives you safer operating speed,
better reliability and lower TCO. | |
SSD news nand flash and nvm news latency reasons
for fading out DRAM in the VM remix How many extra days
does it take to make 60 layer nand flash compared to say 30 layers? (3D
nand fab yield - the nth layer tax?) ..... |
summary
In
the future - all nand flash SSDs will have to use adaptive R/W and DSP ECC IP
technologies in their
controller schemes in
order to be able to use newer generations of denser flash memory. Among other
things these adaptive R/W techniques can magnify
reliability and
performance while
improving SSD design
efficiency and reducing
cost.
As
we go through the transition
years - all the safe assumptions which you thought you knew about flash SSDs
and suppliers will change (again). | |
..... |
The interesting thing about
NVMdurance's IP is that it delivers endurance amplifying results using a
lightweight runtime controller.
But this doesn't stop you getting
even better results by adding DSP correction as an additive process. |
| various conversation with NVMdurance | | |
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| So you want
x3 (TLC) and 3D? |
Editor:- January 23, 2015 - Even if you already
thought that adaptive
R/W and DSP was an essential way for getting usable SSDs out of smaller 2D
nand flash - then there are even more reasons for using this technology on the
journey in 3D.
That's the conclusion you'll come away with after seeing
DensBits's paper (presented at the 2014
Flash Memory Summit) called
the
Necessity for a Memory Modem in 3D Memories (pdf)
Among other
things in this paper:- DensBits says that the scope for inter-cell interference
grows from 8 identifiable routes in 2D to 26 for each cell in 3D.
But
memory modem technology (DensBits's branding for their collection of adaptive
R/W DSP IPs) will (over and above everything it already does for 2D)
intelligently decouple read operations according to the severity of read
operations expected in the new 3D architectures - and even supports the notion
of TLC (x3) within 3D. (Which "needs state of art decoder and signal
processing".)
Their conclusion? - Memory Modem technology is
required for 3D NAND scaling ...read
the article |
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..... |
| "The variability of
the LDPC decode time is a function of how many iterations it takes to decode the
data from the flash and can be upto 20 microseconds." |
| the latency
implications of DSP ECC (May 15, 2014) | | |
..... |
| years ago - in -
SSD market
history |
Anobit samples 1st Memory Signal Processing
flash SSDs
Editor:- June 15, 2010 - Anobit
announced
it is sampling SSDs based on its patented Memory Signal Processing technology
which provide
20x improvement in operational life for MLC SSDs in high IOPS server
environments.
Based on proprietary algorithms that compensate for the
physical limitations of NAND flash, Anobit's technology (a variation of
adaptive R/W
and DSP ECC) extends standard MLC endurance from approximately 3K
read/write cycles to over 50K cycles - to make MLC technology suitable for
high-duty cycle applications.
This guarantees drive
write endurance
of 10 full disk writes per
day, for 5 years. | | |
. |
 |
| Above - Erase Pulse Control -
NAND
Reliability Improvement with Controller Assisted Algorithms in SSD (pdf) -
a paper by SK hynix
at the Flash memory Summit
(August 2013) |
. |
| "How long before we
get to clinical trials?" |
| ...from -
flash care schemes -
will Brand X flash care make your SSD live longer? (Brand Y has better tv ads.) | | |
. |
How adaptive is the SSD
behavior to changes within itself?
All SSDs rely on processing data
about the quality of the memory as part of their normal data integrity
operations.
They wouldn't work without it.
But some companies have SSD IP sets in which knowledge about different
parts of the SSD can be optimized and fed back to control and enhance SSD
functionality over and beyond the standard accepted SSD function block
boundaries.
The degree to which this passing of the intelligence
(regarding the state of past and future anticipatable data flows, priorities
of the application and the flash array's own readiness and healthiness
condition) can impact behavior in other parts of the SSD - is what I call
adaptive intelligence flow symmetry. |
| 11 Key Symmetries in
SSD design | | |
| . |
| LSI says it pays to get a
2nd opinion from LDPC |
Editor:- August 13, 2013 - in a presentation
today at at the Flash Memory
Summit -
the
Nibbles and Bits of SSD Data Integrity (pdf) - LSI explained why
reserving the use of LDPC to deal mostly with read error retries (and also
later in the operating life of flash cells) can be a pragmatic design choice.
And
instead of applying different strengths of
ECC for fixed
physical block sizes - the company says another approach is to have variable
sized virtual blocks - which effectively means that better cells carry lower ECC
overhead.
...Later:- In November 2013 -
LSI began sampling the
SF3700
SSD controller (pdf) - which included elements of adaptive DSP in its design
as well as the unique ability to be configured as either a
small
architecture or large architecture controller. | | |
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| How big was the
thinking in this SSD's design? |
Does size really does matter in SSD
design?
By that I mean how big was the mental map? - not how many
inches wide is the SSD.
The novel and the short story both have their
place in literature and the pages look exactly the same. But you know from
experience which works best in different situations and why.
When
it comes to SSDs - Big versus Small SSD architecture - is something which was
in the designer's mind. Even if they didn't think about it that way at the time.
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For designers, integrators,
end users and investors alike - understanding what follows from these simple
choices predicts a lot of important consequences. ...read the article | | | |
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