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StorageSearch.com / SSD news / May 2014
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PMC blog discusses latency implications of DSP ECC IP in SSD controllers

Editor:- May 15, 2014 - Latency in LDPC-based Next-Generation SSD Controllers is a new blog by Stephen Bates, Technical Director, PMC who says - "The variability of the LDPC decode time is a function of how many iterations it takes to decode the data from the flash."

In his article Stephen says that the minimum number of iterations is 1, typical is 4 and maximum is 20.

To relate that to latency - he says assume for sake of illustration that each iteration takes a microsecond.

Editor's comments:- you can see how those numbers can start to stack up and make inroads into the design of fast SSD controllers.

That's one of the reasons you've got so many different generations of flash memory circulating in the same market today.

The higher the capacity of the SSD - the greater the economic incentive to use newer smaller flash geometries. But those require more complex controller management (to guarantee data integrity) so that incurs greater design complexity and NRE.

PMC's market is the enterprise - but these DSP flash concepts are used in industrial markets too. In fact that's where they originated. Bu in industrial SSDs it can still be sometimes cheaper to deploy more expensive SLC memory in low capacity designs - due to the simpler requirements of the associated controller technology and therefore also lower demands for power hold up time too.

PS - in an earlier blog in this series - Stephen Bates (whose PhD was in signal processing) - revisits the reasons why the SSD market needs to consider the design freedoms which come from using complex DSP flash IP - and he gives examples of the tradeoffs. Such as 50% better endurance with LDPC codes using identical flash - or gaining usable capacity by using weaker codes.

BTW the industry changing possibilities of these technologies for reshaping the economies of SSDs were reviewed in my 2012 article - Adaptive flash care management & DSP IP in SSDs What is it? Who does it? and why?
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LDPC error codes are very effective but suffer from an error floor.

Validating and investigating the design of possible solutions for SSDs requires massively parallel hardware resources - which in turn introduces the risk of noise errors from the simulation engine itself.

Here's how we do it at PMC.
Hardware/Software Co - Simulation for Error Floor Detection in LDPC (pdf) - PMC whitepaper at Flash memory Summit - August 2014
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Decloaking hidden segments in the enterprise
Editor:- Some of the world's leading SSD marketers have confided in me they know from their own customer anecdotes that there are many segments for enterprise flash arrays which aren't listed or even hinted at in standard models of the enterprise market.

Many of these missing market segments don't even have names.

Hey - that means SSD-world is like a map of the US before Lewis and Clark.

If you're a VC should this make you anxious or happy?

If you're a user - maybe that's why no one is delighting you in the way you think you deserve.

That's what led me to write my new article.