click to visit home page
leading the way to the new storage frontier .....
disk writes per day in enterprise SSDs
DWPD ....
image shows Megabyte's hot air balloon - click to read the article SSD power down architectures and acharacteristics
SSD power loss ..
storage security articles and news
SSD security ..
SSD symmetries article
SSD symmetries ..
image shows Megabye the mouse reading scroll - click to see the top 30 solid state drive articles
more SSD articles ...

SSD Controllers and IP

by Zsolt Kerekes, editor

SSD Controllers and IP define the personality of the SSD

LSI SandForce SSD processors - click for more info
the awards winning silicon
accelerating world's leading SSDs
from Seagate
Controller architecture and effective implementation
processes transform unreliable me-too memory chips
into the diverse range of application optimized (or not)
SSDs which you can see in the market today.

SSD news
processors in SSDs
SSD reliability - articles
SSD interface glue chips and IP
SSD endurance myths and legends
how fast can your SSD run backwards?
some thoughts about SSD customization
Why size matters in SSD design architecture
Adaptive R/W and DSP ECC IP for flash SSDs
should we set higher expectations for memory systems?
What were the big SSD ideas to learn and unlearn in 2016?
how the market came to care so deeply about the identity of SSD controllers (classic article)
SSD controller news (extracted from SSD news)
NVMdurance awarded US patent for Adaptive Flash Tuning

Editor:- March 21, 2017 - NVMdurance today announced that it has been granted US patent 9,569,120 for Adaptive Flash Tuning.

CNEX Labs has amassed $60 million for new SSD controller

image shows mouse at the one armed bandit - click to see VC funds in storage
VCs in SSDs
Editor:- March 15, 2017 - CNEX Labs today announced its Series C round of financing which brings total funding to date over $60 million. The company will use the funding for mass production and system integration for lead customers of its NVMe-compliant SSD controllers for hyperscale markets. The new controllers will enable full host control over data placement, I/O scheduling, and other application-specific optimizations, in both kernel and user space.

See also:- adaptive intelligence flow symmetry (1 of 11 Key Symmetries in SSD design).

controllernomics - joins the memory latency to do list

Editor:- February 20, 2017 - As predicted 8 years ago - the widespread adoption of SSDs signed the death warrant for hardware RAID controllers.

Sleight of hand tricks which seemed impressive enough to make hard drive arrays (RAID) seem fast in the 1980s - when viewed in slow motion from an impatient SSD perspective - were just too inelegant and painfully slow to be of much use in true new dynasty SSD designs.

The confidence of "SSDs everywhere" means that the data processing market is marching swiftly on - without much pause for reflection - towards memory centric technologies. And many old ideas which seemed to make sense in 1990s architecture are failing new tests of questioning sanity.

For example - is DRAM the fastest main memory? No - not when the capacity needed doesn't fit into a small enough space.

When the first solutions of "flash as RAM" appeared in PCIe SSDs many years ago - their scope of interest was software compatibility. Now we have solutions appearing in DIMMS in the memory channel.

This is a context where software compatibility and memory latency aren't the only concerns. It's understanding the interference effects of all those other pesky controllers in the memory space.

That was one of the interesting things which emerged in a recent conversation I had with Diablo Technologies about their Memory1. See what I learned in the blog - controllernomics and user risk reward with big memory "flash as RAM"

Fujitsu says in-memory dedupe before writes to flash can double best write speed

Rackmount SSDs click for news and directory
rackmount SSDs
Editor:- December 5, 2016 - Fujitsu today announced the development of a high-speed in-memory data deduplication technology for use in all-flash arrays. The method decides if there is enough time to search for duplicates in the flash array while retaining the data in cache (low load condition). If so then writes to the flash array are only performed after dedupe. Fujitsu says that for some workloads where there are many duplications such as virtual desktops this can improve the user experience.

Mobiveil's Universal NOR Controller Allows SoC Designers to Leverage Adesto's EcoXiP Flash Memory

image shows mouse building storage - click to see industrial SSDs article
industrial SSDs
Editor:- November 30, 2016 - Mobiveil today announced it is working with Adesto Technologies to enhance the memory in low capacity intelligent IoT systems.

Incorporating Mobiveils U-NFC controller to control the new Adesto EcoXiP flash will provide SoC designers an eXecute-in-Place solution that more than doubles the performance of alternative approaches using standalone NOR-Flash memory.

Silicon Motion has SD 5.1 flash controller for Android market

Editor:- November 21, 2016 - Silicon Motion today announced the "world's first merchant SD 5.1 controller solution."

"Android Smartphone shipments accounted for more than 85% of the worldwide market share, and 70% to 80% of these phones have microSD slots," said Nelson Duann, Senior VP of Product Marketing at Silicon Motion, "With the SM2703 controller (2000 / 650 random R/W IOPS on a single TLC die) now supporting SD 5.1, our partners can rapidly bring to market a new generation of SD cards to enable a much better user experience and extend the usability of the Android smartphones."

See also:- SSD controllers, storage market research

patent in China for NVMdurance's flash software

Editor:- August 31, 2016 - NVMdurance today announced it has been granted a patent in China related to its endurance optimization software.

There are several aspects to the company's multi-stage lifecycle endurance management.

life steps imageDuring the memory characterization and design phase its Pathfinder software determines multiple sets of viable flash register values, using a custom-built suite of machine-learning techniques.

Then in production, controllers which use its Navigator firmware choose which of these predetermined sets to use for each stage of life to ensure that the flash lasts as long as possible.

new memories? new security risks?

Editor:- August 4, 2016 - Is remanence a security risk in persistent memory? That's the topic of my new blog here on

If you aren't yet ready to evaluate these new SCM style NVDIMMs you might think you can skip this article.

That's OK as long as you already were aware that that data recovery has always been feasible in old style DRAM too. the article

IP-Maker releases Gen 3 NVMe PCIe reference design

Editor:- July 11, 2016 - for designers of PCIe SSDs - IP-Maker has released its new Gen 3 NVMe PCIe reference design which is based on the VC709 evaluation kit by Xilinx.

It's integrated with Xilinx's Virtex-7 PCIe Gen3 hard IP and a soft DDR3 controller. The UNH-IOL NVMe compliant design uses a x4 lanes configuration.

DIMM wars at battery scale - FLC from Marvell

Editor:- May 12, 2016 - When thinking about SSD / SCM DIMM wars - most of the buzz in the past year has been focused on the impacts of replacing DRAM with flash at the enterprise server and cloud levels. But the same concepts can be applied (albeit with different efficiency gains) at the implementation level of battery powered embedded devices and wearables.

In a recent blog - How Marvell FLC Redefines Main Memory - by Hunglin Hsu, VP - Marvell provides authoritative examples of the replacement ratios possible in a phone design.

A strategic lesson to guide future designers is that even while getting a 50% power consumption reduction (due to flash as RAM) it is also feasible to increase application performance at the same time because the software can work with a larger memory capacity (due to the lower cost of flash bytes).

Among other things Hunglin says - "With FLC, better performance can be achieved by reporting to the operating system a larger than physically implemented main memory. The operating system is thus less likely to kill background apps, which is why the fast app switching is possible. The FLC hardware does all the heavy lifting in the background and frees up the tasks of the operating system." the article

data noise reduction techniques in nvm

Editor:- April 22, 2016 - A recently published book - Channel Coding Methods for Non-Volatile Memories (145 pages, $130) cowritten by Lara Dolecek and Frederic Sala University of California, provides an overview of recent developments in coding for nvms, and, by presenting numerous potential research directions, may inspire other researchers to contribute to this timely and thriving discipline.

Editor's comments:- this appears to be focused on the DSP and ECC end of the Adaptive R/W flash care management & DSP IP revolution which during the last 4 years or so has been changing the way that new memory technologies with poor intrinsic data integrity (high noisiness - when viewed from a classical ECC data angle) can be upcycled to construct higher quality, more reliable solid state storage by adaptive and interventionist coding strategies.

2 ASIC roles for PCIe based BiTMICRO SSD controllers

Editor:- March 25 , 2016 - 5 years ago when BiTMICRO unveiled an earlier generation of its high performance enterprise SSD controller architecture - it was clear that their preference was for a chipset which included 2 different types of functionality.

This kind of thinking wasn't unique at that time - as I'd seen similar things in rackmount SSD designs before but (unlike BiTMICRO) those other designs were captive and not offered as COTS SSD controllers.

How many controller chips do you really need for a PCIe SSD?

In a new blog today BiTMICRO explains why its current generation of controllers continues using a 2 ASIC architecture with one acting as a flash array extender and the other as the main PCIe host interface controller.

Among other things the blog says "To increase flash channel bandwidth and capacity, more flash channel expander chips can be instantiated and connected to the main controller."

As noted in the SSD design heresies - SSD vendors often have different implementation architecture approaches which compete in similar application slots. When evaluating different types of offerings it can be useful to ask yourself - which direction is my own design likely to stretch in future? (Towards more performance? lower cost? bigger scale? adjacent application role? etc.) BiTMICRO's blog clarifies where they see their strengths in the market. the article

Hyperstone samples new industrial USB SSD controller

Editor:- February 15, 2016 - Hyperstone is sampling a new USB 3.1 Flash memory controller - the U9 - in a TFBGA-124 package - for industrial applications.

Among other things the ECC engine can correct up to 96-Bit/1KB. Power management features include automatic power-down during wait periods for host data or flash memory operation completion and automatic sleep mode during host inactivity periods.

Editor's comments:- As you'd expect from a USB device it's not intended for heavy write applications - and although some of the data integrity features are suggested to be enterprise compatible - the sustained random write speed for 4KB is 5MB/s (30x slower than the peak sequential write.)

Nevertheless - given the portability of strategic applications and system software between form factors and the convenience of DWPD as a way of grouping SSDs for different roles I asked Hyperstone if they can supply an indicative range of DWPD for the new USB controller (when used with various classes of memory and DRAM size). I got this answer from Axel Mehnert VP Marketing who said this.

"Yes, we can give you such ratings Hyperstone has a web based lifetime estimation tool which can be accessed by registered users of our site. There you can play with several settings and Flash configurations in order to get DWPD data also correlating to several different access patterns."

new SSD Bookmarks by Cadence

Editor:- February 5, 2016 - You all know Cadence right?

So what set of online resources do you think they'd recommend to newcomers who want to learn more about SSDs? (BTW - Rules of this game disallow mouse links in the mix.)

You don't have to guess. I asked. And you can see Cadence's suggested SSD Bookmarks today in the new series on

Marvell is first to ship Host Memory Buffer feature in NVMe SSD controller

Editor:- January 5, 2016 - Marvell today announced expansion of its NVMe SSD controller technology to support Host Memory Buffer (HMB), an NVMe revision 1.2 feature enabling DRAM-less (skinny) flash SSDs to use host memory and achieve performance comparable to SSD designs with regular embedded DRAM but at much lower cost and power consumption.

3 new educational flash blogs

Editor:- December 11, 2015 - Here are some flash SSD blogs I've seen this week which are aimed at educating SSD specifiers in embedded markets.
  • Soft-Decoding in LDPC based SSD Controllers - from PMC-Sierra - includes clear explanations about some of the read again (re-read) recovery strategies which can be used as part of the tool set in adaptive R/W and DSP ECC when things go wrong.

    For example - "Read the same section as the original hard data but use a different set of read threshold voltages inside the NAND."

    These techniques are rarely shared publicly in such detail and are real life optimizations unlike the imaginary techniques I discussed in my 2011 fictional company profile of XLC Disk
  • SSD 101 - Everything You Ever Wanted to Know - aimed at newcomers to the concepts and jargon in industrial SSDs is a new framework overview from Cactus Technologies which links together a bunch of their earlier short blogs. These articles include good diagrams of flash planes, controllers and cells.

    Re the title "SSD 101 etc" - how far it satisfies "everything" you want to know is debatable. But if you're starting out in flash and need the reassurance that the technology background is sound - this series is better than many others I've seen.

Processors in SSD controller design - a new series

Editor:- October 12, 2015 - Coming soon on the mouse site - a new series... aspects of SSD design - processors used in SSDs. This is for those of you who know in your bones that to get the SSD you want - you need to design your own controller.

Datalight's SSD firmware to go into manned spacecraft

Editor:- September 17, 2015 - Datalight today announced that its embedded filesystem (Reliance Nitro) and FTL (FlashFX Tera) have been selected by NASA for use onboard future manned spacecraft being developed as part of the Orion program.

Mirabilis discusses role of deployment level simulation to optimize reliability delivered by SSD controller design tweaks

Editor:- August 16, 2015 - "A diligent system designer can extend the life of an SSD by upto 60% by proper control of over-provisioning, thus reducing TCO" says Deepak Shankar, Mirabilis Design in his recent paper Extending the Lifetime of SSD Controllers (pdf) which discusses the role of application and deployment level simulations to explore the impact of changing brews in controller architectural coctails.

See also:- SSD overprovisioning articles 2003 to 2015

Altera launches adaptive endurance controller for PCIe SSD market

Editor:- June 23, 2015 -Altera today announced availability of a new flash controller reference design for the NVMe PCIe SSD market which uses adaptive R/W endurance.

The Arria 10 SoC (pdf) which includes among other things an integrated dual-core ARM processor uses flash IP from Mobiveil and NAND optimization software from NVMdurance to simplify the design of gen 3 PCIe SSDs having 7x better endurance than classical non adaptive designs.

Editor's comments:- Since the market criticality of adaptive DSP flash controller techniques for enterprise SSDs began to emerge in 2011 and then clarified in a big way in 2012 - it has become an essential capability for most product lines. This standard product from Altera fills a much needed gap in their offerings.

The SSD controller page in past years.

Readers doing research on the evolution of the SSD controller market have tiold me they find it useful to see archived versions of this news page.

The internet archive lets you see the SSD controller page from 2009 to the present day.

Other options are archived storage and SSD news from 2000.

Or put the words "SSD controller" into the site search box below. (It's all here on this site if it was important in the SSD market.)
storage search banner
SSD SoCs - on
firming up the reference design
raw chip memory...
how much as SSD?
how much as memory?
cloud adapted memory systems
SSD ad - click for more info
In the current state of the SSD market it's possible for systems companies to use array level software to deliver efficiencies and reliabilities which are as good and sometimes much better than any controller company can deliver in the best solo SSD while the array company uses me-too or not very impressive controllers in each SSD.

The consequences are that the SSD controller market will fragment into:-
  • lowest cost for standard functions, and
  • ability to customize (and collaborate) by software
  • outstanding capability for high value markets in a solo SSD
The array market will become a can't sell zone for any controller company which tries to over-deliver unwanted features (and fool's gold value) in its solo SSD nodes.

And at the same time well see systems companies doing more customization of controllers.

That means controller companies which do introduce standout features will have to figure out where they stand with respect to future standardization and customization. editor in conversation (August 2016)

custom matters in SSDs
SSD market changes in 2016
CPUs in the post modern SSD era
controllernomics - is that even a real word?
SSD ad - click for more info
DRAM stayed stuck in the Y2K era of enterprise latency and that's why its future will go the same way as the 15K hard drive.
latency reasons for fading out DRAM
SSD SoC / IP vendors list


Anobit (acquired by Apple)

ASMedia Technology



Crocus Technology

Cypress Semiconductor



ECC Technologies



Faraday Technology

Global Unichip

Greenliant Systems




ITE Tech






Northwest Logic


NxGn Data


Phison Electronics




Renice Technology

Sage Micro



Silicon Integrated Systems

Silicon Motion



DiskOnChip family from M-Systems
DiskOnChip® - flash solid state disks
upto 2G bytes from M-Systems
Notes from SSD market history

The DiskOnChip - shown above - from M-Systems
(no longer in business) - was the 1st "SSD chip" ad
featured on It ran here from
April 2004 to February 2006. The DiskOnChip had
been launched a long time before that - in 1994!
Surviving SSD sudden power loss
Why should you care what happens in an SSD when the power goes down?

This important design feature - which barely rates a mention in most SSD datasheets and press releases - has a strong impact on SSD data integrity and operational reliability.

This article will help you understand why some SSDs which (work perfectly well in one type of application) might fail in others... even when the changes in the operational environment appear to be negligible.
image shows Megabyte's hot air balloon - click to read the article SSD power down architectures and acharacteristics If you thought endurance was the end of the SSD reliability story - think again. the article
"after numerous delays, a new wave of next-generation, nonvolatile memories are finally here. One technology, 3D NAND, is shipping and gaining steam. And 3 others - Magnetoresistive RAM, ReRAM and even carbon nanotube RAMs - are suddenly in the mix"
Mark LaPedus, Executive Editor - Semiconductor Engineering - in his new blog - Gaps in the memory hierarchy have created openings for new types of memory - which is flavored with some strong opinions from leading memory analysts. (September 16, 2015)
What's the best way to design a flash SSD?

and other questions which divide SSD opinion
More than 10 key areas of fundamental disagreement within the SSD industry are discussed in an article here on called the the SSD Heresies.
click to read the article - the SSD Heresies ... Why can't SSD's true believers agree upon a single coherent vision for the future of solid state storage? the article
How (and when) did the SSD market change from...

Who cares? - to - You care! - about the identity of SSD controllers?
Imprinting the brain of the SSD
1.0" SSDs 1.8" SSDs 2.5" SSDs 3.5" SSDs rackmount SSDs PCIe SSDs SATA SSDs
SSDs all flash SSDs hybrid drives flash memory RAM SSDs SAS SSDs Fibre-Channel SSDs is published by ACSL