Kerekes, editor -StorageSearch.com|
Controllers and IP define the personality of the SSD
architecture and effective implementation
processes transform unreliable
the diverse range of application optimized (or not)
SSDs which you can
see in the
SSD interface glue
chips and IP
SSD endurance myths
fast can your SSD run backwards?
some thoughts about SSD
Why size matters in
SSD design architecture
and DSP ECC IP for flash SSDs
should we set
higher expectations for memory systems?
What were the big
SSD ideas to learn and unlearn in 2015?
how the market came to
care so deeply about the identity of SSD controllers (classic article)
controller news - here on StorageSearch.com
|Non-Balanced Wear Leveling
- a paper by Renice|
Editor:- July 28, 2016 - Renice Technology
recently published a paper -
Wear Leveling Algorithm (pdf) - which outlines the thinking behind a
specific technique in its industrial SATA3 SSD controller - model
- to improve
upto 3x compared to traditional methods.
This is one of the several techniques used in this
controller to overall get a 20x improvement in lifespan when using
the article (pdf)
Editor's comments:- Ever since the
first flash devices were evaluated it has been known that some blocks are much
better than others.
As an example in this paper Renice shows that
in a modern 16GB MLC flash chip - even after just 10 P/E cycles the controller
is able to see a 3x difference between the fastest and average program time and
over 30% difference between the slowest and fastest read times.
quality of wear resistance tells you something which can be used to grade
Renice's non-balanced wear leveling algorithm leverages
these naturally occurring process variations so that "the higher
wear resistance blocks are selected to be erased more times while the lower
ones get protected instead."
IP-Maker releases Gen 3 NVMe PCIe reference design
July 11, 2016 - for designers of
PCIe SSDs - IP-Maker has released
its new Gen 3 NVMe PCIe reference design which is based on the VC709
evaluation kit by Xilinx.
integrated with Xilinx's
PCIe Gen3 hard IP and a soft DDR3 controller. The
NVMe compliant design uses
a x4 lanes configuration.
DIMM wars at battery scale - FLC from Marvell
May 12, 2016 - When thinking about
SSD / SCM DIMM
wars - most of the buzz in the past year has been focused on the impacts of
replacing DRAM with
flash at the
server and cloud
levels. But the same concepts can be applied (albeit with different
efficiency gains) at
the implementation level of battery powered embedded devices and wearables.
a recent blog -
Marvell FLC Redefines Main Memory - by Hunglin Hsu, VP
provides authoritative examples of the replacement ratios possible in a phone
A strategic lesson to guide future designers is that even
while getting a 50% power consumption reduction (due to flash as RAM) it
is also feasible to increase application performance at the same time because
the software can work with a larger memory capacity (due to the lower
cost of flash
Among other things Hunglin says - "With FLC, better
performance can be achieved by reporting to the operating system a larger than
physically implemented main memory. The operating system is thus less likely to
kill background apps, which is why the fast app switching is possible. The FLC
hardware does all the heavy lifting in the background and frees up the tasks of
the operating system." ...read
data noise reduction techniques in nvm
22, 2016 - A recently published book -
Methods for Non-Volatile Memories (145 pages, $130) cowritten by Lara Dolecek
and Frederic Sala
University of California, provides an overview of recent developments in
coding for nvms, and, by presenting numerous potential research directions, may
inspire other researchers to contribute to this timely and thriving discipline.
comments:- this appears to be focused on the DSP and ECC end of the
flash care management & DSP IP revolution which during the last 4 years
or so has been changing the way that new
memory technologies with
poor intrinsic data integrity (high noisiness - when viewed from a classical
ECC data angle) can be upcycled to construct higher quality, more reliable
solid state storage by adaptive and interventionist coding strategies.
2 ASIC roles for PCIe based BiTMICRO SSD controllers
March 25 , 2016 - 5
years ago when BiTMICRO
unveiled an earlier generation of its high performance enterprise SSD
controller architecture - it was clear that their preference was for a chipset
which included 2 different types of functionality.
This kind of
thinking wasn't unique at that time - as I'd seen similar things in
designs before but (unlike BiTMICRO) those other designs were captive and not
offered as COTS SSD
How many controller chips do you really need for a
a new blog
today BiTMICRO explains why its current generation of controllers continues
using a 2 ASIC architecture with one acting as a flash array extender and the
other as the main PCIe host interface controller.
Among other things
the blog says "To increase flash channel bandwidth and capacity, more flash
channel expander chips can be instantiated and connected to the main controller."
As noted in the SSD
design heresies - SSD vendors often have different implementation
architecture approaches which compete in similar application slots. When
evaluating different types of offerings it can be useful to ask yourself - which
direction is my own design likely to stretch in future? (Towards more
performance? lower cost? bigger scale? adjacent application role? etc.)
BiTMICRO's blog clarifies where they see their strengths in the market. ...read the
Hyperstone samples new industrial USB SSD controller
February 15, 2016 - Hyperstone
is sampling a new USB 3.1 Flash memory controller - the
- in a TFBGA-124 package - for industrial applications.
things the ECC engine can correct up to 96-Bit/1KB. Power management features
include automatic power-down during wait periods for host data or flash memory
operation completion and automatic sleep mode during host inactivity periods.
comments:- As you'd expect from a
USB device it's not
intended for heavy write applications - and although some of the data integrity
features are suggested to be enterprise compatible - the sustained random write
speed for 4KB is 5MB/s (30x slower than the peak sequential write.)
- given the portability of strategic applications and system software between
form factors and the convenience of
DWPD as a way of grouping
SSDs for different roles I asked Hyperstone if they can supply an indicative
range of DWPD for the new USB controller (when used with various classes of
memory and DRAM size). I got this answer from Axel Mehnert VP
Marketing who said this.
"Yes, we can give you such ratings
Hyperstone has a web based lifetime estimation tool which can be accessed by
registered users of our site. There you can play with several settings and
Flash configurations in order to get DWPD data also correlating to several
different access patterns."
new SSD Bookmarks by Cadence
Editor:- February 5,
2016 - You all know Cadence
So what set of online resources do you think they'd recommend
to newcomers who want to learn more about SSDs? (BTW - Rules of this game
disallow mouse links in the mix.)
You don't have to guess. I asked.
And you can see
suggested SSD Bookmarks today in the
Marvell is first to ship Host Memory Buffer feature in NVMe SSD
Editor:- January 5, 2016 - Marvell today
expansion of its NVMe SSD controller technology to support Host Memory Buffer
(HMB), an NVMe revision 1.2 feature enabling DRAM-less (skinny) flash
SSDs to use host memory and achieve performance comparable to SSD designs with
regular embedded DRAM but
at much lower cost and power consumption.
3 new educational flash blogs
Editor:- December 11,
2015 - Here are some flash SSD blogs I've seen this week which are aimed
at educating SSD specifiers in embedded markets.
in LDPC based SSD Controllers - from PMC-Sierra -
includes clear explanations about some of the read again (re-read) recovery
strategies which can be used as part of the tool set in
and DSP ECC when things go wrong.
For example - "Read the
same section as the original hard data but use a different set of read threshold
voltages inside the NAND."
These techniques are rarely shared
publicly in such detail and are real life optimizations unlike the imaginary
techniques I discussed in my 2011 fictional company profile of
101 - Everything You Ever Wanted to Know - aimed at newcomers to the
concepts and jargon in
is a new framework overview from Cactus Technologies
which links together a bunch of their earlier short blogs. These articles
include good diagrams of flash planes, controllers and cells.
title "SSD 101 etc" - how far it satisfies "everything"
you want to know is debatable. But if you're starting out in flash and need the
reassurance that the technology background is sound - this series is better
than many others I've seen.
Processors in SSD controller design - a new series
October 12, 2015 - Coming soon on the mouse site - a new series...
SSD design - processors used in SSDs. This is for those of you who
know in your bones that to get the SSD you want - you need to design your
PMC-Sierra agrees to be acquired for $2 billion
October 6, 2015 - PMC-Sierra
has agreed to be acquired by Skyworks
for $2 billion it was
Specifically, we plan to leverage PMCs innovative storage
systems, flash controllers, optical switches and network infrastructure
solutions to expand our engagements with some of the worlds leading OEMs and
ODMs as well as
data center customers said David J. Aldrich,
chairman and CEO of Skyworks.
Micron acquires stealth mode NVMe SSD controller company - Tidal
Editor:- October 3, 2015 - Micron has acquired
Tidal Systems (a stealth mode
controller company whose home page has the statement "Enabling PCIe NVMe
Flash Storage Development" according to a news report by Tom's
Hardware which suggests that the acquired company's controller
technology is adaptive
Editor's comments:- In June 2015 I summarized the
weaknesses of Micron's flash controller technology and commented on the oddity
of its not having made any significant enterprise
in the preceding 12 to 18 months. In which I said "Micron's enterprise
storage strategy has not met the basic needs of Micron as a memory company. It
doesn't have any strong SSD architectures and systems roadmaps of its own."
- in the same article in
a February 2014 note - I wrote about "Micron's DIMM SSD accelerator
product gap / opportunity / threat"... That was recently addressed with
the recent announcement of Optane.
So that leaves just one main
outstanding action on the future Micron "to do list" - from the SSD
analysis in their profile page here on the mouse site - the acquisition of a
rackmount SSD reference architecture or product line.
Datalight's SSD firmware to go into manned spacecraft
September 17, 2015 - Datalight
today announced that its embedded filesystem (Reliance
Nitro) and FTL (FlashFX
Tera) have been selected by NASA for use
onboard future manned spacecraft being developed as part of the
Mirabilis discusses role of deployment level simulation to
optimize reliability delivered by SSD controller design tweaks
August 16, 2015 - "A diligent system designer can extend the life of an SSD
by upto 60% by proper control of over-provisioning, thus reducing TCO"
Design in his recent paper
the Lifetime of SSD Controllers (pdf) which discusses the role of
application and deployment level simulations to explore the impact of
changing brews in controller
overprovisioning articles 2003 to 2015
the most significant development in the enterprise flash market
in the past 3 years
Editor:- August 13, 2015 - "Diablo's
Memory1 is the most significant development in the enterprise flash market in
the past 3 years."
That was my assessment of the recent
by Diablo of its
which repurposes non volatile nand flash as volatile RAM.
not strictly speaking an SSD technology this stretch and repurposing of
standard industry flash reveals that
was not the end of the enterprise flash controller innovation story. The new
product, technology and competitors are discussed in a blog on StorageSearch.com -
DIMM wars in
SSD servers how significant is Diablo's Memory1?
Altera launches adaptive endurance controller for PCIe SSD market
June 23, 2015 -Altera
availability of a new flash controller reference design for the
NVMe PCIe SSD market
which uses adaptive
10 SoC (pdf) which includes among other things an integrated dual-core ARM
processor uses flash IP from
Mobiveil and NAND
optimization software from
simplify the design of gen 3 PCIe SSDs having 7x better endurance than
classical non adaptive designs.
Editor's comments:- Since the
market criticality of adaptive DSP flash controller techniques for enterprise
SSDs began to emerge in 2011 and then clarified in a big way in 2012 - it has
become an essential capability for most product lines. This standard product
from Altera fills a much needed gap in their offerings.
|In the current state of the
SSD market it's possible for systems companies to use array level software to
deliver efficiencies and reliabilities which are as good and sometimes much
better than any controller company can deliver in the best solo SSD while the
array company uses me-too or not very impressive controllers in each SSD.|
consequences are that the SSD controller market will fragment into:-
- lowest cost for standard functions, and
- ability to customize
(and collaborate) by software
market will become a can't sell zone for any controller company which tries
to over-deliver unwanted features (and
fool's gold value)
in its solo SSD nodes.
- outstanding capability for high value markets in a solo SSD
And at the same time well see systems
companies doing more customization of controllers.
That means controller companies which do introduce standout features
will have to figure out
where they stand
with respect to future standardization and customization.
(August 2016) in reply to some questions.|
big versus small
new SSD ideas
in 2015 and
sudden power loss|
|Why should you care
what happens in an SSD when the power goes down? |
This important design
feature - which barely rates a mention in most SSD datasheets and press releases
- has a strong impact on
SSD data integrity
This article will help you understand why some
SSDs which (work perfectly well in one type of application) might fail in
others... even when the changes in the operational environment appear to be