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Everspin Technologies

Everspin Technologies is the global leader in developing and manufacturing standalone and embedded magnetic-based memory (MRAM) and integrated magnetic sensors. A growing number of leading corporations in the computing, storage, industrial and office automation markets have adopted Everspin MRAM to enable their most advanced products. www.everspin.com

see also:- Everspin / MRAM - mentions on StorageSearch.com

SSD application notes for ST-MRAM

the upside and downside of hold-up caps in MIL flash SSDs

editor's comments:- Everspin operates in the non flash part of the non volatile memory market and recently entered the PCIe SSD market.


Everspin Technologies - mentions in SSD market history

In April 2010 - Everspin Technologies announced it is sampling a 16Mb MRAM

In August 2013 - Everspin Technologies announced it has closed a Series B financing, raising $15 million to accelerate growth in the enterprise storage market. Investors in the round included New Venture Partners, Sigma Partners, Lux Capital, Draper Fisher Jurvetson, and Epic Ventures.

In August 2014 - Everspin Technologies announced a design win for its ST-MRAM in enterprise PCIe SSD class products being designed by Mangstor.

In January 2015 - Western Digital was among the investors in $29 million series B funding for Everspin.

In August 2015 - Aupera launched the world's first M.2 SSD which used Everspin's MRAM (instead of flash) as the nvm.

In September 2016 - Everspin filed for an IPO.

In March 2017 - Everspin began sampling an NVMe PCIe SSD based on its ST-MRAM.
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Soft-Error Mitigation for PCM and STT-RAM
Editor:- February 21, 2017 - There's a vast body of knowledge about data integrity issues in nand flash memories. The underlying problems and fixes have been one of the underpinnings of SSD controller design. But what about newer emerging nvms such as PCM and STT-RAM?

You know that memories are real when you can read hard data about what goes wrong - because physics detests a perfect storage device.

A new paper - a Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories (pdf) - by Sparsh Mittal, Assistant Professor at Indian Institute of Technology Hyderabad - describes the nature of soft error problems in these new memory types and shows why system level architectures will be needed to make them usable. Among other things:-
  • scrubbing in MLC PCM would be required in almost every cycle to keep the error rate at an acceptable level
  • read disturbance errors are expected to become the most severe bottleneck in STT-RAM scaling and performance
MRAM and PCM data integrity issues click to read the article (pdf)
He concludes:- "Given the energy inefficiency of conventional memories and the reliability issues of NVMs, it is likely that future systems will use a hybrid memory design to bring the best of NVMs and conventional memories together. For example, in an SRAM-STT-RAM hybrid cache, read-intensive blocks can be migrated to SRAM to avoid RDEs in STT-RAM, and DRAM can be used as cache to reduce write operations to PCM memory for avoiding WDEs.

"However, since conventional memories also have reliability issues, practical realization and adoption of these hybrid memory designs are expected to be as challenging as those of NVM-based memory designs. Overcoming these challenges will require concerted efforts from both academia and industry." ...read the article (pdf)

Editor's comments:- Reading this paper left me with the confidence that I was in good hands with Sparsh Mittal's identification of the important things which need to be known.

If you need to know more he's running a one day workshop on Advanced Memory System Architecture March 4, 2017.

See also:- an earlier paper by Sparsh Mittal - data compression techniques in caches and main memory
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"When tech companies invest in sales then we can infer something useful about them."
Zsolt Kerekes, editor - StorageSearch.com (May 11, 2017) in an email congratulating Annie Flaig Senior VP of Worldwide Sales - Everspin Technologies on the announcement of her appointment in the new role.

See more in SSD news - MRAM? - should we still be calling this - "emerging memory"?
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MRAM's fitness for high altitude and hot environments discussed in a blog by Everspin
Editor:- February 22, 2017 - A new blog - MRAM earns its stripes in HiRel applications - by Duncan Bennett, Product Marketing Manager at Everspin lists some of the intrinsic characteristics of MRAM and their advantages for roles in aerospace applications. Among other things Duncan Bennett says:-
  • "MRAM memory bits are immune to the effects of alpha particles."
  • "MRAM outperforms other non-volatile memory technology when it comes to data retention at high temperatures."
...read the article

Editor's comments:- this article only talks about the virtues of MRAM but another recent paper which I mentioned recently in SSD news - a Survey of Soft-Error Mitigation Techniques for Non-Volatile Memories (pdf) - raised doubts about the simplicity of using MRAM due to its soft error sensitivity to read disturb errors.

Admittedly this was looking at an enterprise memory context where the more memory you have the sooner you are likely to witness such errors. But it's just my way of reminding you that there are no magic products in the memory ecosystem.

To be fair Everspin's article also mentioned that some mission critical customers use screening processes to select "hardened" MRAM - because - just as with traditional memories - some devices are just better than others.
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Everspin files for IPO
Editor:- September 9, 2016 - Everspin Technologies has filed for an IPO.

Among other things in the form S-1 the company said - "Our 5 largest end customers together accounted for 34% of our total revenue for the six months ended June 30, 2016, but none of these customers individually accounted for more than 10% of our total revenue during the period."
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"We are still the only company shipping any kind of MRAM product... We have shipped over 50 million units. ... our new silicon on 40nm is a 256Mb chip."

Phillip LoPresti, CEO - Everspin
Inside The MRAM (September 2015)
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Everspin's MRAM is one tier of the non volatile caching technology used in Skyera's rackmount SSD systems. Skyera had not long before been acquired by WDC.
Western Digital invests in Skyera's MRAM supplier - January 26, 2015
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world's first M.2 MRAM SSD
Editor:- August 13, 2015 - Everspin Technologies and Aupera Technologies today announced the launch of the worlds first all MRAM storage module in the M.2 form factor.

The AupM001 is equipped with Everspin's non-volatile, high endurance, 64 Mb DDR3 ST-MRAM devices and a PCIe backhaul interface. AupM001's capacity is 32MB and among other uses is used in Aupera's all Flash Array system for parity check and as a hardware accelerated engine for specific applications that require low latency and high performance.
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Everspin quadruples MRAM chip R/W
Editor:- February 26, 2013 - Everspin Technologies today announced it will sample the first of a new family of MRAM chips in Q2.

The MR10Q010 (1Mb in a 16 pin SOIC) has a quad SPI serial interface instead of the single line interface offered in earlier MRAM devices.

This makes it more attractive for applications which need the simplicity of no wear-out non volatile memory and fast write performance in low capacity and small footprint applications.
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