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3D nand fab yield - the nth layer tax?

are more dimensions of analysis needed to get a clearer picture of future 3D nand successions?
Zsolt Kerekes, editor - July 3, 2017

If you're trying to predict and anticipate how the supply of next generation nand flash will ramp up in the next year compared to how you've seen memory successions before then the 3D nand flash market has presented many problems of analysis and interpretation.

As nand flash is still the dominant memory technology used inside over 99.9% of SSDs and as the switch from planar 2D to 3D was pitched as the lowest risk solution to continue supplying the growing need for more flash storage - because memory geometry shrinks had gone about as far as they dared go - there has been much uneasiness and disquiet recently in markets which use these memory chips about the shortages which have been the most obvious sign that progress has not been entirely plain sailing.

Many blogs in the SSD market in recent quarters have focused on the technology and business impacts (such as higher costs and lost opportunities to make SSDs) with various degrees of informed speculation and analysis.

What's really going on?

One of the key secrets of memory makers ever since the earliest days of semiconductor memory is that the yields and manufacturability problems are kept closely guarded secrets because they are competitively very sensitive. So the only way we're going to get an accurate "from the horse's mouth" picture of everything which has contributed to making these tranistions so bumpy is after the underlying problems have been solved which the memory industry will signal in the traditional manner by promises of lower prices and quicker deliveries.

One of the best summaries I've seen of the flash industry's predicament is a blog I recommended here in March 2017. Shootout at Yokkaichi - the NAND Industry at the Crossroads by William Tidwell, Semiconductor Analyst who regularly writes about such things on Seeking Alpha. And I make no apology for repeating that here.

Another blog on the current 3D successor generations which I think many of you would find interesting is the newer (June 21, 2017) - NAND Market Hits Speed Bump by Mark LaPedus, Executive Editor - Semiconductor Engineering.

Mark's blog provides a snapshot of the current 3D succession plans by the leading memory makers. And if - like me - you've already seen more than enough of such pretty 3D memory pictures you might be tempted to just click away. But I found 2 observations in that article particularly interesting .

First from Applied Materials which is a strategic supplier of wafer level production, inspection and testing technologies used by memory chip makers. AMC expects wafer starts for 3D nand to be in the region 500,000 to 700,000 wspm (wafer starts per month) by the end of 2017 - which is about 60% more than a year ago.

The other interesting comment came from Greg Wong, President - Forward Insights.

Greg's point is that while going from 2D to 3D gave the industry the same kind of aerial bit density improvement that the industry got accustomed to with decades of Moore's Law geometry shrinks - the shape of the bits per chip roadmap curve - as you add more layers of 3D to an industry which is already using double digit layers of deposited memory - is not going to be the same for successive N+ layer generations.

When you add more layers to a 60 layer memory - for example - the next increment can be any arbitrary level which makes sense from the manufacturing and marketing points of view. The next steps don't have to be x2 jumps as they often were in 2D - because the process challenges are different.

One important thing which has been missing from most of the articles which I've seen about 3D nand successor generations is any clear picture of how much longer each 3D chip spends in the fab compared to earlier 2D memory generations.

The promise of the initial switch to 3D memory was you get more memory bits for a similar number of wafer starts and invested wafer fabs.

It's clear that adding each memory layer adds more processing time. It would be useful to have an idea of how that scales - and the risk reward factors of yield due to rejects and rework - because that would give customers in the SSD industry more realistic expectations of how they can interpret the other data they get from the memory industry. (Investments in new fabs, and roadmaps on the number of layers and virtual bit density TLC, QLC etc.)

A "time served in the fab" model for incremnental layers would provide more confidence in future generations of memory roadmap too.

"feed the fab" - productivity issues

After writing the above I thought I'd better look around and see if I can point readers to articles which discuss wafer fabs, yield and time spent in the fab in more details. As I expected - due to the business sensitivity of such insights - the papers I found were rather old or talked about DRAM etc rather than flash. But they do give you a feel for some of the strategic issues - which if you haven't had close contact with the semiconductor business will tell you more about the tactics and strategies used in the production flow.
  • Enhancing the Effectiveness of Cycle Time Estimation in Wafer Fabrication-Efficient Methodology and Managerial Implications (pdf) - 2014 - includes this interesting comment...

    "Estimating and shortening the cycle time of each job is an important task to maintain a competitive edge in the DRAM industry. For example, Samsung, implemented the short cycle time and low inventory (SLIM) method to estimate the cycle times and WIP (work in progress) levels for various manufacturing steps, so that a more effective control of the factory was possible. As a result, the average cycle times of some DRAM products were reduced from more than 80 days to less than 30 days, bringing Samsung a benefit of about $1 billion.
  • Benchmarking Semiconductor Manufacturing (pdf) - 1997 - says this...

    "Using older-generation processing equipment on newer process flows may make the achievement of world-class defect densities much more difficult than if newer equipment is used. While yields may be lower when employing older processing equipment, capital costs are lower as well, and so the strategy might turn out to be economically competitive or even superior to the strategy that employs solely new processing equipment."

    This is relevant given the prequel to the 3D memory direction story in which all the memory companies had been losing money and reluctant to invest in entirely new equipment.
But I still wasn't satisfied with that. I know people in the industry today who can tell you more if they choose to. But how to reach out to them?

So I did this post on my linkedin connection (and as it was July 4 I didn't expect to get many answers quickly) but I was wrong about that.

3D nand fab yield - the nth layer tax?

How many extra days does it take to make 60 layer nand flash compared to say 30 layers?

And how does that compare to planar?

I mean the incremental time in the fab for manufacture and test. Let's call it the nth layer tax...

Having a good grasp on these numbers will help memory market analysts and systems customers get a more realistic feel for how the memory market can ramp up to successor generations assuming any stable reference start point of fab investment and wafer starts.

It's clear from the current shortages that we need more realistic expectations about the manufacturing impacts of moving up the layers. On the other hand the pressure of market demand and longer times in the fab have been good incentives to bring forward QLC.

Here are some of the comments.
  • Rob Peglar Senior VP & CTO, Symbolic IO said.

    "Zsolt - there is no single answer to this question. Highly dependent on layer geometry, aspect ratio, materials used, deposition method, bits per cell, etc. Dozens of factors, truth be told. Plus, it would be highly unusual for the exact same characteristics and methods to be used in two different products (# of layers). Sorry for not being of more help :-) but that's the reality. No easy answers."
  • Jon Haswell - VP Firmware at SK hynix memory solutions said.

    "This whole question is at the heart of the cooperative strategy of each NAND vendor. To the first order everybody knows how to build 3D NAND now, the question is how to build it cheaper, trading off geometry versus yield versus FAB time/steps. Nobody is likely to publish their roadmap for this as they don't want to tip their hand, good or bad to their competitors.

    Best the analysts can probably do is to plot the historical trends on die capacity, die size and volume each vendor supplies to determine the approximate yielded FAB capacity."
  • It takes about 5 weeks to process 64 layer by 64 layer 3D nand flash (with 2017 fab technology) according to a later video by Sang-Yun Lee, President & CEO - BeSang (July 23, 2017) which compares the incremental manufacturing costs to the company's proposed 3D super nand technology.
what are memory makers doing to increase manufacturing capacity?

A later post - Micron Continues to Outperform the Memory Industry As A Whole (July 31, 2017) by Robert Castellano on Seeking Alpha includes among other things a summary of what Hynix, Samsung and Micron are thought to be doing to increase memory output along with bit growth in the most recent quarter.

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whatever did really happen to ULLtraDIMM?
Editor:- August 1, 2017 - The recent history and market adoption of NVDIMMs is similar to the early messy history of the SSD market in that fascinating products appear at one time and then fail to get traction to remain in the market in successive memory generations.The reasons are similar:-
  • Competition from other ways of getting similar work done.

    In the case of NVDIMMs not just other types of raw native memory but SSDs in other form factors too. Such as PCIe which can be deployed to give approachingly similar performance.
  • Software support which is meaningful.

    Without a competitive and capacble software base which can recognize the latent strengths of the new memory technology - the results you get are never as good as the raw technology can deliver. Or if the early software is good enough but the capability is single sourced that deters market growth due to fears of being locked into a proprietary supplier.
A new blog - an NVDIMM Primer (Part 1 of 2) (July 25, 2017) by Jim Handy - founder Objective Analysis offers this explanation for market demise of the ULLtraDIMM.

Jim says "Both SanDisk and IBM later abandoned the technology, which I have heard was due to performance issues stemming from the lack of an interrupt pin on the DDR3 bus." the article

In my own contemporaneous coverage of that product I wrote about other factors which I thought at the time indicated weaknesses in that first generation (of its kind) product. These were:-
  • there was a SATA bridge inside the DIMMs between the flash and the DDR3 logic. The result was system level performance which was not as great as you might expect - compared to native enterprise PCIe SSDs.
  • for about a year there were legal wrangles surrounding patents associated with the design which scared off other wouldbe adopters and at one stage a court order which stopped shipments.
  • the ULLtraDIMM guzzled power - so you couldn't just drop it into a standard motherboard socket without checking that the power tracks had sufficient copper.
  • the ULLtraDIMM product was not the "reason to buy the company" product line in 2 successive company acquisitions of its flash technology parents SMART then SanDisk - so it was just one of several SSD products lines which were let go.
As you can see there were certainly enough bullets to wound (if not kill) the first generation ULLtraDIMM. But its unsung (less sung about) creator had learned the lessons and produced a superior follow up product.

related blogs on

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after AFAs - what's the next box?

NV DIMMs - the flash backed DRAM kind

the road to DIMM wars and Diablo's Memory1

where are we heading with memory intensive systems and software?

controllernomics and risk reward ratios with big memory "flash as RAM"

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VCs in SSDs
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the SSD news archives
Can you trust SSD market data?
what's RAM really? - RAM in an SSD context
Can you tell me the best way to get to SSD Street?
WekaIO compares cloud storage pools to IBM FlashSystem
Editor:- July 12, 2017 -WekaIO - a cloud storage software company today emerged from stealth and announced details of its cloud-native scalable file system which the company says can deliver performance comparable to rackmount SSDs / AFAs.

Editor's comments:- The notable thing for me in this announcement was that WekaIO uses a performance benchmark compared against an IBM FlashSystem 900 (the decendant of the RamSan world's fastest storage systems from TMS.)

WekaIO says "Utilizing only 120 cloud compute instances with locally attached storage, WekaIO completed 1,000 simultaneous software builds compared to 240 on IBM's high-end FlashSystem 900. The WekaIO software utilized only 5% of the AWS compute instance resources, leaving 95% available to run customer applications."

That's an ambitious positioning statement and offers users a glimpse into the kind of performance they can get by using flash assisted cloud services. Like other modern SSD fabric software software - "WekaIO eliminates bottlenecks and storage silos by aggregating local SSDs inside the servers into one logical pool, which is then presented as a single namespace to the host applications."
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SSD software ....
SSD symmetries article
SSD symmetries ..
Flash Memory
flash & nvm ....
Rackmount SSDs click for news and directory
rackmount SSDs ..
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SSD news - July 2017

more archived news
3D nand will face ceiling of vertical scaling soon

Editor:- July 28, 2017 - It takes about 5 weeks to process 64 layer by 64 layer 3D nand flash (with 2017 fab technology) according to a recent video (11 minutes) by Sang-Yun Lee, President & CEO - BeSang (July 23, 2017) which compares the incremental manufacturing costs to the company's proposed 3D super nand technology.

Among other things Sang explains why he thinks the 3D nand bandwaggon will be unable to reduce SSD storage costs in future vertical scaling generations. He says this roadmap was - "A mistake by smart people." ...see the video

Editor's comments:- If San is right with his prognosis on 3D nand - it has ramifications for the expectations about the costs of SSDs in the next few years.

As BeSang has been busy with linkedin blog posts and videos promoting the purported superiority of of 3D super nand and 3D super DRAM I asked the company.

Is Besang looking for flash makers to license the technology? Or will you make devices of your own?

BeSang told me - "BeSang is a fabless NAND product maker and doing IP licensing for DRAM and eDRAM. SK Hynix is the first licensee of 3D Super-DRAM."

Embedded NVM - à la mode in September

Editor:- July 28, 2017 - The South of France isn't a location which would have sprung to my mind as the most obvious place to look for an event related to non volatile memories and embedded designs. But in that respect I was wrong. The Leading Edge Embedded NVM Workshop will take place September 25 to 27, 2017, in Gardanne (Aix en Provence area, France).

The 3 day program of presentations (pdf) includes speakers from around the world. Here are some of the titles of the papers to give you an idea of the spread of topics.
  • "Inkjet - Printed Flexible Conductive Bridge RAM"
  • "Secure Characterisation of the OxRAM Technology."
  • "Voltage Compatibility of ReRAM operation with CMOS"
  • "Scaling and Demonstration of a 28nm Logic-Process-Compatible Split-Gate Flash Memory Technology"

IC Insights reports record breaking memory ASPs

Editor:- July 20, 2017 - A recent research note about the memory market by IC Insights puts an interesting spotlight on memory shipments.

Among other things IC Insights says:- "DRAM, unit shipments are actually forecast to show a decline this year. Moreover, NAND shipments are forecast to increase only 2%."
memory price data from IC Insights
When it comes to price expectations IC Insights says this.

"Even though DRAM ASP growth is forecast to slow in the second half of the year, the annual DRAM ASP growth rate is still forecast to be 63%, which would be the largest annual rise for DRAM ASPs dating back to 1993 when IC Insights first started tracking this data. The previous record-high annual growth rate for DRAM ASP was 57% in 1997. For NAND flash, the 2017 ASP is forecast to increase 33%, also a record high gain. (In the year 2000, the predominantly NOR-based flash ASP jumped 52%)."

For those who need much more information IC Insights publishes a 250 page report ($4,090) which includes various free monthly updates. more

Editor's comments:- One message to take away from this is that as memories have been transitioning to the next multiple of 3D layers the chip throughput from the industry's legacy wafer fabs has stayed the same or gone backwards due to the extra time taken to reliably make those extra layers to create higher bit density memories.

Related guides here on with an SSD perspective.

Swissbit to show low power industrial M.2 NVMe PCIe SSD at FMS

Editor:- July 20, 2017 - Swissbit today said it will show a prototype of a new low power industrial M.2 NVMe PCIe SSD at the Flash Memory Summit next month.

Swissbit says - "Whilst the popular 4-lane/8-channel NVMe products are tuned for the highest data rate, Swissbit's N-10 has a different focus: With its 2-lane/4-channel architecture, N-10 can offer more than double the performance of an SSD with SATA 6Gb/s interface, and significantly reduces power consumption."

Virtium says it's no longer a matter of if, but when, NVMe supplants AHCI in industrial SSDs

Editor:- July 19, 2017 - Last week I noticed a new blog from Virtium - NVMe: Taking a Seat at the Industrial-Embedded Table - and that prompted me to ask - "Can Virtium tell me about any new industrial equipment or application roles in which the availability of NVMe PCIe SSDs was the deciding factor for their customer and for the feasibility of the project?"

A spokesperson for Virtium said - "The concept of NVMe is new to the industrial-embedded space, for the very reasons we cited in the blog – that the capacity needs simply didn't demand PCIe performance that be offset by the penalties it would exact, namely software incompatibility and increased power consumption. Industrial-embedded-system designers, therefore, are just now starting to look at the NVMe-SSD "marriage" in a different light, given how IIoT data is going to require a lot more storage. So, at this point we can't cite any decided-upon designs that will definitely feature NVMe SSDs. However, we can say many of the Virtium customers we have spoken with about this concept agree that it's no longer a matter of if, but when, NVMe supplants AHCI as the SSD interface in certain industrial-embedded designs."

See also:- this is not your Grandfather's industrial SSD market

Storage Visions Conference 2017 - call for papers etc

Editor:- July 18, 2017 - One of the big changes in the storage events calendar this year is that the annual Storage Visions Conference has moved from its traditional January (CES compatible) location and timing up to October. Apart from the more convenient date that may also reflect that the content of the conference has expanded and adapted in recent years to cover all aspects of storage such as the enterprise and cloud instead of just the consumer stuff which you'd expect from its proximity to a big consumer show.

The 16th annual 2017 Storage Visions Conference will be held Monday, October 16, 2017 in Milpitas, CA.

Listed among the many reasons you might be interested in attending include:- "Understand new applications for storage class memory" and "Find new methods for reducing power consumption".

Speaking and panelist submissions are open through August 15, 2017 and you can submit a speaking proposal at: This linked page also includes contact details.

Editor's comments:- I've been watching the Storage Visions Conference grow in stature in our industry (outlasting many others which sparng up in the early 2000s) and I admire the dedication and work of its creator Tom Coughlin.

Having said that one of the odd things which puzzled me about SV 2017 (and which I mentioned to Tom this week) was the unclarity of the typeface and dischordant contrast of the raw text compared to the background in the banners and logos which have been designed to attract interest in the conference.

Storage Visions  Conference 2017 example of the banners for the eventI've included one example to the right of this here.

And you can see more variations and judge the clarity or otherwise of the designs for yourself on the SV 2017 banners page here.

I'm color blind so maybe some of that is just me. But isn't English words set against Ancient Egyptian heiroglyphics just text on text? The background is too interesting and draws attention away from the text. While the letters in the text are too hard to instantly recognize as their contrast changes from top to bottom.

This is the kind of readability issue which I've been warning advertisers against since the 1990s. And if you're interested in such web communication matters see my seldom updated site Marketing Views.

On the other hand - I hope that the seriousness of the topics and the event itself will help you see past the idiosyncasy of this year's Storage Visions banner. And if you want to spread the word then you now know where to look.

Hey you're looking at a site which has mice in its logo. So I trust you can see beyond such superficial factors.

WDC secures advance warning of Toshiba nand asset changes

Editor:- July 14, 2017 - Western Digital annnounced today it has obtained a court order to prevent Toshiba transferring its interests in jointly held nand flash assets without giving prior notice to WDC's SanDisk subsidiary (which shares some of these resources) "to ensure that the issue is preserved for arbitration."

A follow up story in Japan Times clarifies that the notice period is "2 weeks" and furthermore says "Toshiba lawyers have contended in court documents that any sale of the chip division was not expected to close until early next year, at the earliest."

See also:- Toshiba's forced memory sale - timeline of past stories

3D eTLC adoption - blog by Toshiba

Editor:- July 17, 2017 - The long saga of naughty flash in the enterprise (2004 - 2017) had already embraced 3D TLC by 2015 (in low DWPD arrays) - but I have to confess that although I had seen the prefix "e" used before for MLC I didn't realize this hardening veneer of marketing jargon had been deemed worthy enought to have been been recycled unto the next generation of memory too - as eTLC.

But there it was - eTLC - large as life in a recent blog - MLC Flash in a 3D World – What is it Good For? by Jeremy Werner VP of SSD Marketing Toshiba America Electronic Components - so I suppose it must be true.

Among other things Jeremy's blog mentions that early (2009) doubts by some commentators about the efficacy of MLC in the enterprise were wrong! and in recent years the market enabling factor for newer generations of MLC, TLC etc is that there is now "Better understanding of workloads..." the article

Which prompted me to say on linkedin

"Good article placing naughty flash in context. As Jeremy says the enterprise didn't understand the workloads in storage when flash SSDs began to be used in arrays. Now we have a much more sophisticated market which can deploy any type of new memory to a latency and cost per gigabyte role where it is most cost effective."

Looking ahead it's tempting to see a pattern here. So in the years to come will we see eQLC?

In reality this type of "enterprise" differentiation of flash grades has long been meaningless at the technical level because it makes much more difference to the system reliability what the controller does and the software and the ratio of (NV)RAMcache that's available for data manipulation before it gets written to flash.

I guess that memory manufacturers have to choose names to differentiate their many selections of flash and "e" has been useful and is easy to deploy. And is less likely to be misunderstood than choosing other letters such as for example "b" for "better" as in bTLC.

the reliability difference in solo industrial SSDs

Editor:- July 14, 2017 - Reliability is one of the concerns which got me interested in SSDs in the late 1980s, and the other factor was raw speed - sometimes - but not always - both in the same project. And different ways of looking at reliability is one of the recurring themes which I notice in stories about the industrial SSD market.

Earlier this year I had noticed a statement in one of the customer case studies on the web site of Cactus Technologies which talked about having delivered 200,000 high reliability flash storage cards to a customer "without a reported failure". And from time to time I wondered what did that really mean?

So this week I asked Steve Larrivee, VP Sales & Marketing at Cactus what was the time period behind the story?

Steve said - "The 200,000 cards were delivered over a 2 year period over 5 years ago without one reported failure."

Editor's comments:- I thought this was an impressive retrospective story and for customers with applications where the reliability of each solo SSD is critical it's a more convincing positioning statement about the design and manufacturing capabilities of the SSD creator than any forward reaching promises can be.

After our exchange of emails Steve wrote a new blog about this - Would Memory Failure Be Catastrophic to your business? - which included additional anecdotal failure rates for the same application which happened when the customer switched to a lower cost memory SSD design from a competing high quality supplier.

trust and services marketing related to enterprise SSD systems
why was it so hard to compile a simple list of military SSD companies?

Viking offers mid life kicker to SAS SSD array market

Editor:- July 11, 2017 - Viking today announced it is shipping the industry's highest capacity 3.5" SAS SSD.

The dual port UHC-Silo SSD series has 50TB planar MLC capacity, endurance rating of 1 DWPD for 5 years, idle power consumption under 10W and active power usage of only 16W.

Editors' comments:- with 6Gps SAS rather than 12, and relatively low DWPD this is aimed at the capacity and power optimized part of the rackmount SSD market.

In 2012 I speculated that SAS would become the new SATA for array SSDs once the 2.5" PCIe SSD market reached a competitive critical mass - because quite frankly SAS can't compete on latency. Whereas there is a huge ecosystem which is comfortable with managing arrays of dual port SAS drives. So as long as the drives are big enough in capacity terms - there will be an appetite for them.

Looking at the datasheet - at first glance - an apparent weakness of the new UHC-Silo SSDs is the lack of any mention of power fail protection. But the best place to engineer such protection for enterprise storage can be at the rack level. So in that respect saving space and cost at the drive level can be regarded as a prudent customization.

Looking at the capacity claim in Viking's press release...

"There is no higher capacity SSD solution available today than the UHC-Silo SSD" said Hamid Shokrgozar, President, Viking Technology."...

Seagate demonstrated 60TB SAS SSD prototypes last August but if Viking really is shipping 50TB now that suggests that those wanting to extend the market life of SAS arrays and related software can look in new directions.

Later:- in August 2017 - we learned where Viking's mysterious "SAS SSD" IP had come from. See:- sauce for the SSD box gander - Nimbus enters SAS SSD controller market

new controller enables low latency persistent PCIe memory

Editor:- July 10, 2017 - IP-Maker today announced the release of its new PCIe Gen 3NVMe reference design based on the Xilinx VC709 evaluation kit. IP-Maker has implemented NVMe management as a full hardware IP, able to process it in less than 1µS. The company says it has introduced the new IP to support low latency persistent memories on the PCIe bus.

24 Gb/s SAS and other interesting milestones in Demartek's new interface comparison guide

Editor:- July 7, 2017 - Demartek has published a new version of its Storage Networking Interface Comparison Guide which includes timelines, speed ratings and roadmaps for the most popular interfaces used in storage system. Among other things the SAS section notes that "the first 24 Gb/s SAS plugfest is expected to occur in 2H 2017."

60,000 wafers scrapped in memory fab

Editor:- July 6, 2017 - Given the current memory shortages it was interesting to see a report in DIGITIMES yesterday which said that 60,000 12" wafers had been scrapped recently in a Taiwan based foundry owned by Micron.

Although that foundry makes DRAM the context of that wafers number is that it's about the same as the worldwide wafer starts (for all manufacturers) of 3D nand in a single month. The cause of the scrappage was corrected in a later story.

Samsung announces more investment in memory fabs

Editor:- July 5, 2017 - An article in the Guardian - mentions among other things an announcement that Samsung "will invest nearly $18 billion in its chip business."

Editor's comment:- Haha for the very same amount some other lucky buyer will get Toshiba's memory business (and patents).
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read more about this 19 year old SSD icon
The announcement that Nimbus (otherwise better known for its multipetabyte capable rackmount SSD systems) was - in effect - entering the SAS SSD market as a 3.5" drive reference design supplier was not such a big surprise to me.

More interesting was the "aha! moment"- when it became clear that it was indeed Nimbus whose SSD controllers were at the heart of 2 recent (similar sounding but competing) high capacity SAS SSD product launches in recent weeks from Viking and SMART Modular.
sauce for the SSD box gander
AccelStor NeoSapphire  all-flash array
1U enterprise flash arrays
InfiniBand or 10GbE iSCSI or 16G FC
NeoSapphire series - from AccelStor
SSD news in July's of yore
  • July 2000 - SST launched a 64MB PATA SSD on a chip as a replacement for hard drives in space constrained and reliability sensitive appliances.
  • July 2006 - Samsung said it was readying a 4GB PATA flash SSD which would be supported as a cache in notebooks using the ReadyBoost feature of the Windows Vista operating system.
  • July 2007 - SanDisk announced that IBM was saving 1,500 watts per server rack and getting much faster performance by using 2.5" SATA SSDs in its new BladeCenter instead of hard drives.
  • July 2008 - To speed up the power-up to boot time Texas Memory Systems announced that its new ultrafast 512GB 4U RAM SSD used an internal flash array instead of hard drives from which data was transparently restored to RAM.
  • July 2010 - Fusion-io revealed that its PCIe SSDs had been used to accelerate the production of many 3D movies including :- Alice in Wonderland, Avatar, How to Train a Dragon and Clash of the Titans.
  • July 2012 - Signs that the SSD industry was getting volume came in an announcement that the industry's most popular SSD controller - the SandForce range - was shipping at the rate of over 1 million devices each month.
  • July 2013 - Micron began sampling 16nm nand flash memory chips. They were 128Gb MLC. In the next 4 years which followed the flash industry chose to go up in layers and up in bits per cell to get more bits per chip rather than down in nm geometries.

If you're one of those who has suffered from the memory shortages it may seem unfair that despite their miscalculations and over optimimism the very companies which caused the shortages of memory and higher prices - the major manufacturers of nand flash and DRAM - have been among the greatest beneficiaries.
consequences of the 2017 memory shortages

Targa Series 4 - 2.5 inch SCSI flash disk
2.5" removable military SSDs
for airborne apps - GbE / SATA / USB
from Targa Systems

The industry will learn a lot about the "goodness" of new memory tiering products by stressing them in ways which the original designers never intended.
RAM disk emulations in "flash as RAM" solutions

Despite the bewildering range of products in the market - the performance characteristics and limitations of ALL flash SSDs are determined by a small set of of architectural parameters.
understanding flash SSD performance limitations

after AFAs? - the next box
Throughout the history of the data storage market we've always expected the capacity of enterprise user memory systems to be much smaller than the capacity of all the other attached storage in the same data processing environment.

after AFAs - click to read rhe articleA new blog on - cloud adapted memory systems - asks (among other things) if this will always be true.

Like many of you - I've been thinking a lot about the evolution of memory technologies and data architectures in the past year. I wasn't sure when would be the best time to share my thoughts about this one. But the timing seems right now. the article

industrial mSATA SSD
industrial grade mSATA SSDs
>2 million write cycles per logical block.
from Cactus Technologies

related guides

Are we there yet?
After more than 20 years of writing guides to the SSD and memory systems market I admit in a new blog on - Are we there yet? - that when I come to think about it candidly the SSD industry and my publishing output are both still very much "under construction". the article

SSD jargon

RAM has changed from being tied to a physical component to being a virtualized systems software idea - and the concept of RAM even stretches to a multi-cabinet memory fabric.
what's RAM really? - RAM in an SSD context

All the marketing noise coming from the DIMM wars market (flash as RAM and Optane etc) obscures some important underlying strategic and philosophical questions about the future of SSD.
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I think it's not too strong to say that the enterprise PCIe SSD market (as we once knew it) has exploded and fragmented into many different directions.
what's changed in enterprise PCIe SSD?