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SSD Jargon - Megabyte rows his boat to  a sign saying  flipper channel 3 miles

dipping into the waters of SSD jargon

by Zsolt Kerekes, editor -
Little words can have with big meanings in the world of SSDs.
They affect price, performance, reliability and user happiness.

This article collects together short descriptions of many commonly used SSD technical terms (but not all). You may also find it useful to put the words you're having trouble with into the site search box below - to get an idea of the context.

SSD marketers also like to invent new words or blend and recycle existing reals words when naming new products, companies and technologies. I've assembled real world examples in my article series - Branding Strategies in the SSD Market
SSD news / the Top SSD Companies / an A to Z of articles
SSD Endurance - Is a term used in the context of flash memory and SSDs and is more verbosely called "Write Endurance."

Simple explanation... The number of write cycles which can be performed by any block of flash is limited due to physics and technology imperfections which eventually make the data storage process unreliable.

That number varies according to the type of flash (MLC is usually 10x worse than SLC) and according to the memory generation and also whether it has been designed (or selected) for high endurance. And also whether the memory is 2D or 3D, the size of RAM cache, intelligence of the software etc.

Typical raw values of flash endurance in the market today (2016) using classical controller techniques range from as low as 1,500 cycles upto 100,000 cycles. (Raw endurance of millions of cycles is also possible in rare custom industrial applications which use very large geometry - low capacity flash.)

Many techniques can be deployed in SSD controllers to mitigate the effects of endurance - and extend usable life of a raw memory array by upto many orders of magnitude compared to the intrinsic life of a dumb flash array without such a controller.

  • flash wars in the enterprise SSD market- shows how every generation of flash memory was at first resisted by enterprise array designers. But each one was eventually made to behave using a variety of hardware and software design techniques.
  • adaptive R/W and DSP ECC in flash - discusses techniques used in newer controller designs (since about 2012) which provides better endurance than classical controllers by locally grading and assessing the quality of flash in real-time instead of depending on industry meta data for timing pulses.
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SSD Garbage Collection is an important background process in flash SSD controllers.

Some editors and software vendors (who don't understand flash technology) mistakenly attribute a long term slow down in some SSDs to fragmentation - when really the issue is the ratio of resources allocated to Garbage Collection.

In well designed products which have reserved enough CPU power, internal R/W bandwidth and over-provisioning this "performance degradation" does not occur - or is minimal. For example systems from Violin Memory.

The term Garbage Collection was 1st used in 2002 - in an article we published about flash SSD reliability. Here's the definition below from that article.

The "Garbage Collection Process" eliminates the need to perform erasure of the whole block prior to every write. The "Garbage Collection process" accumulates data marked for erase as "Garbage" and perform whole block erase as space reclamation in order to reuse the block.
MLC (Multi Level Cell) is a term used in the context of flash memory and flash SSDs to describe how the storage charge in a single floating gate transistor cell is interpreted by the logic system.

In traditional digital systems, the change in state (of a voltage, current or charge) is interpreted as being either 1 of 2 distinct levels - "0" or "1" - which is where we get the term binary logic from. Such flash cells are called SLC (Single Level Cell).

In an MLC memory chip the stored charge is interpreted as a range of values (0 to 3), (0 to 7) etc - which depends on the ability of the discrimator circuits surrounding the memory array to reliably tell the difference between levels.

The logical memory capacity of a such a cell is 2 bits, or 3 bits etc - where the bits are binary.

Discriminating multiple levels is difficult to achieve technically - because it involves an analog to digital conversion process - and due to manufacturing tolerances the same charge may not represent the identical value in another part of the chip.

There are also various factors which make the process unrepeatable - by dumping charge into the cell when adjacent parts of the chip are being written to, by leakage from the cell into the substrate over time, and by damage in the transistor material due to successive writes (endurance).

MLC designers overcome these problems (which become harder in each shrink generation) by wrapping blocks of memory in protective error correction and detection codes.

Because the charge in an MLC cell is interpreted as 2x, 4x etc more data than in the same geometry level SLC chip - MLC is much more sensitive to age and wear-out factors than SLC. That's why oems typically quote an endurance figure which is 10x lower.

Why go to all this trouble? - MLC memory provides capacity which is 2x, 4x etc lower cost than SLC. That competitive advantage is a compelling argument in many applications.

Throughput is similar for SLC and MLC SSDs. Although the extra R/W complexity in MLC is intrinsically slower than SLC - the data nibble going in or out of the cell is worth more informational bits than in SLC - which compensates.

Another refinement of MLC is x3 aka TLC (triple level cell) nand flash - which offers 8 distinct states in a single cell - equivalent to 3 binary bits of storage.

see also:- MLC - editor mentions, how the enterprise adoption of flash changed from 2004 to 2017
"Silent Errors" - is a term used to describe uncorrected data errors in a flash SSD which arise from an incompletely understood, inappropriate or poorly designed data integrity architecture.

Many new products are vulnerable to these errors. For more details see the article:- Data Integrity Challenges in flash SSD Design
SSD Over-Provisioning is a technique used in the design of some flash SSDs. By providing extra memory capacity (which the user can't access) the SSD controller can more easily create pre-erased blocks - ready to be used in the virtual pool.

2 beneficial effects of Over-Provisioning are:-
  • faster overall write IOPS, and
The latter case - is because another use of the extra capacity is to replace bad memory blocks - which occur at both ends of the bathtub curve.

There are wide variations in the percentage of flash over provisioning in different SSD designs. This is discussed in more detail in the article - flash SSD capacity - the iceberg syndrome.
SSD Wear Leveling is a technique used inside flash SSDs to prolong the life of a flash memory array.

Countering the phenomenom called endurance - Wear Leveling processes in the SSD controller keep track of how many erase cycles have been performed on each flash block - and dynamically remap logical to physical blocks using algorithms which spread out the wear over the whole population in the array. Working hand in hand with over-provisioning - bad cells (which wear-out earlier than the median life) can be replaced - considerable extending SSD life.

There are 3 levels of wear leveling used in the best server grade SSDs - static, dynamic and active.

Rugged & Reliable Data Storage: Solid-State Flash Disks overview

Increasing Flash Solid State Disk Reliability

SSD Myths and Legends - "write endurance"

is eMLC the true successor to SLC in enterprise flash SSD?
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SSD Write Amplification - is a term popularized by SiliconSystems in various flash SSD related articles and press releases.

Gary Drossel, a VP at SiliconSystems defines it as follows. "Write Amplification - is a measure of the efficiency of the SSD controller. Write amplification defines the number of writes the controller makes to the NAND for every write from the host system. Long, continuous writes map over this mismatch, but most embedded/ enterprise applications do not stream data. Instead, they transfer data in a series of shorter, more random transactions."

It's the difference in ratio between the number of theoretical writes you think that your application does to a flash SSD - compared to what actually happens - due to OS or other software - which is often outside your control. Write Amplification can be a serious problem - because it can invalidate calculations related to endurance. SiliconSystems says - the best thing to do is measure it - rather than estimate it. Their SSDs can be used as tools to do this - because they perform real-time internal logs of write cycles.
SSD Write Attenuation - is a term coined by the editor of

It is the opposite effect of Write Amplification - and reduces the amount of writes done to the SSD compared to what you expect. This kind of out-of-sequence recognition, and reordering of packets before writes usually requires a non volatile RAM or similar memory inside the SSD controller.

Beneficial side effects of Write Attenuation are:-
  • lower wear-out of the flash SSD, and
  • (often) faster random IOPS - because the nv cache doesn't have to be flushed out as inefficiently - as in the case of unprotected RAM caches.
Skinny, Regular and Fat flash SSDs

These are new terms (July 2009) proposed in an article called - RAM Architectures in flash SSDs to describe RAM/flash ratios in flash SSDs.
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ASAPs (Auto-tuning SSD Accelerated Pools of storage )

This is a new term (November 2009) coined by to describe a product category which includes products like the following:- Although aimed at different markets, and having different interfaces, what they all have in common is their ability to self-tune.

In effect - "ASAPs eliminate waits for the SSD Hot-Shot / Hot-Spot Engineer ..."
11 key symmetries in SSD design - defines 11 new SSD jargon terms and provides a unified overview of SSD architecture.
Legacy SSD and New Dynasty SSD - are ways of classifying enterprise acceleration SSDs by the architecture of the storage environment they were designed to go into.

This nomenclature - was introduced in in September 2010 in this article - A new way of looking at the Enterprise SSD market.
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I recently discussed the memory boom bust cycle with a non technical reader who asked me to explain why high volume semiconductor memory makers get into the situation of oversupply and lossy pricing.
introduction to semiconductor memory boom-bust cycles
Flash Memory Basics - for enterprise SSD buyers
Editor:- February 3, 2010 - a new article - Flash Memory Basics - posted today by blogger Brad Diggs looks like it could be part of an educational series laying the groundwork for Sun Microsystem's PCIe SSD product family.

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disk writes per day in enterprise SSDs SSD news since 1998 M2 SSDs SSD training and education directory
DWPD ...... SSD news ...... M.2 SSDs ...... SSD education
  • PIM - processing in memory - (which first appeared in SSD news in April 2018) is a synonim for the earlier (2014) in-situ SSD/memory processing.
  • SLC, MLC, TLC, QLC, OLC - each word to the right doubles the distinguishable levels in a memory cell. There has always been initial resistance in the enterprise to each new memory generation until reliability has been demonstrated. TLC is now considered respectable in the right DWD context. QLC (quad level cells) are the next thing.

    pSLC - pseudo SLC - is different in that it doesn't denote a physical memory type - pSLC is an operating mode whereby any raw flash memory which can discriminate more than 2 distinct levels in a cell (such as MLC, TLC, OLC) is programmed as though it only had 2 levels like SLC. Throwing away the extra capacity makes pSLC designated blocks faster to program and more reliable. See more about these tradeoffs in - a Survey of Techniques for Architecting SLC/MLC/TLC Hybrid Flash Memory based SSDs (27 pages pdf)
New Improved SSD Formula!
news flash:- XLC Disk has launched a new fast-enough fat cache eMLC SSD ASAP on a PCIe form factor with 200K (truly symmetric) R/W IOPS. High endurance and data integrity are achieved by using DSP adaptive flash management with 3 levels of wear-leveling despite light over-provisioning. The new SSD has industry leading write attenuation and fast garbage collection, has UBER better than 1 sector in 1019 eliminating the risk of silent errors. The no SPOF SSD has internal FT features such as RAID, plane failure management and chipkill - and can fail-over the entire flash array to an alternate PCIe host without loss of data. Designed for mission critical server apps - the SSD has strong protection against sudden power loss which doesn't rely on supercaps....
do you understand all the ingredients in the SSD news headlines?

What are the factors holding back faster adoption in the SSD market?

That's been a constantly recurring topic in my discussions with SSD designers and oems in the past 18 years.

Now, if you're a manufacturer of hard disk drives you may think that the SSD market is racing along fast enough already - and doesn't need any more help from me.

But User Education has always come up as the most important SSD market accelerant.

Back in 1998 when we published the 1st real-time updated directory of SSD oems - the most important part of the education mix seemed to be - What were the benefits of application speedup - if you could afford SSDs?

Later, when I published my definition - What's a Solid State Disk? - in 2000 - I didn't think there was much more I could say on this subject.

But in the decade which followed - I told users
  • they could use some flash SSDs in server apps (if they were SLC and had high endurance and good wear-leveling), and then we said
  • they should be extremely cautious when choosing server apps for MLC SSDs. Then some types of MLC were better than others. Or exactly the same MLC - when used with different controllers was more or less reliable.
Confusing, isn't it?

Along the way users have had to learn the differences between RAM SSDs, MLC and SLC flash SSDs - and also hybrids.

In some ways this resembles consumer education about what foods to eat (or not to eat) to maintain a healthy lifestyle. But in the case of SSDs - the foods have been evolving fast and are now forming a bigger part of everyone's diet.

So you need to know more about the ingredients listed on the carton.

Even if you already know all you need to know about endurance, MLC, SLC and wear-leveling - here are 3 new concepts I think you'd benefit from following up in your future reading ...
  • SSD - Write Amplification and Attenuation
  • SSD - Garbage Collection
  • SSD - Over-Provisioning
I never thought users would need to know so much stuff about SSDs. But you do.

You can't rely on your SSD vendors to tell you. Just as you wouldn't base a healthy diet on things chosen randomly from a supermarket shelf - or buy a car just because it's got the right number of wheels. You have to choose your own risk / reward comfort zones in the SSD market too.
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DWPD - in the SSD context is a way of rating endurance and matching application slots to the SSD.

DWPD stands for Diskful Writes Per Day and the associated assumption is that this daily usage figure is good for an operating period of 5 years.

See also:- what's the state of DWPD? - which gives examples of DWPD for various different types of enterprise SSDs from leading vendors.
NVDIMMs - non volatile dual inline memory modules

"DIMMs" has long been established as the collective term for the form factor used in motherboard DRAM modules.

NVDIMMs - as you might guess - hints that although the module has the appearance and plug compatibility of a standard DRAM DIMM - the NV tells you that the memory technology is something else.

The usage of the term NVDIMM has grown to include memory modules which include flash and other types of non volatile memory (and sometimes DRAM as well). And these modules can be used (depending on the internal design and software) as DRAM emulators, RAM SSD emulators, flash backed DRAM, SSDs, tiered memory etc.

In theory a suffix may tell you more. But in reality there are many permutations of products in the market. And to confuse things even further some NVDIMMs are volatile and lose their contents when the power is switched off.

You can find more about the business development, technology and use cases of NVDIMMs in these articles:- Introducing NVDIMM-X (pdf) - an architectural white paper by Xitore which is creating this "-X" technology includes a useful top level list of NVDIMMs.
HMS SSD - Host Managed SSD technology

First used in 2015 by OCZ - in the context of a new range of array oriented SATA SSDs - HMS enables host software to have better visibility and granular control of data movements and house-keeping activity inside the SSD controller.

The name is new - but the concept of this kind of multi-level storage intelligence has appeared under different names in the past (although not as memorable names as HMS.)

Details of scope and implementation vary considerably but the concept's ancestor owes much to the "controller-less" design of the worlds' first PCIe SSDs from Fusion-io. And with different details an HMS concept (3rd generation controller) was implemented in earlier SSDs by Baidu, Memblaze, InnoDisk and Radian Memory.

HMS was called "adaptive intelligence flow symmetry" in my 2012 article - 11 Key Symmetries in SSD design .
ull SSDs - ultra low latency SSDs.

In the circa 2013 period the context usually is related to Memory Channel Storage.

The idea is to implement ultra low latency flash SSDs - similar to but faster than PCIe SSDs - in modules which plug into DRAM compatible sockets.
SSD CPU Equivalency

This term was invented by the editor in 2008 to succintly describe a concept he discovered and used in systems designs in the 1980s and which underpinned his earliest published SSD market adoption model in 2003.

It's related to SSD speedup / acceleration in servers.

For a wide range of applications (in a well designed system) if you take a black box approach and analyze the overall application performance of a computer system - you would not know from external tests whether that system had more CPUs with hard disks or less CPUs with more SSDs. That's SSD CPU Equivalency.

Flash Translation Layer - is the standard term for lumping together the software and hardware IP which interecepts R/W requests for logical flash memory addresses made to the SSD from the apps processor and converts these into actions which do real R/W to the physical memory.

In the simpler days of SLC when flash was intrinsically more reliable - the FTL was a much simpler IP package than it is now.

The FTL - which can operate at many different levels - hides things like bad block management, wear leveling, data integrity etc so that the external software can think it's talking to clean reliable memory.
µSSD, SATAe and SATA Express

These are next step variants of the Serial ATA (SATA) interface standard roadmap.

The new terms came into being in 2011.
  • µSSD - or more correctly "SATA µSSD" - defines the standard pins in an SSD chip (BGA form factor) which support the SATA interface - and which (in theory) makes it easier for systems designers to interchange SSDs from different suppliers.

    See also:- SSDs on a chip
  • SATAe and SATA Express - define the pins for the successor standard for SATA 3 - for a 2.5" form factor. The speedup in the SATAe generation - comes from 2 lanes of PCIe instead of doubling of the 6Gbps speed of SATA 3.

    See also:- 2.5" PCIe SSDs

Cactus 2.5" rugged SLC SSD
military grade 2.5" SATA SLC SSDs
>2 million endurance cycles per block
-45C to 90C / quick erase 512GB in <15S
from Cactus Technologies

SSDserver rank
SSDserver rank is a latency based configuration metric - proposed as a new standard by - which can tersely classify any enterprise server - as seen from an SSD software perspective - by a single lean number rating from 0 to 7. the article

Scale-up - refers to architecture that uses a fixed controller resource for all processing. Scaling capacity happens by adding storage shelves up to the maximum number permitted for that controller.

Scale-out - refers to architecture that doesnt rely on a single controller and scales by adding processing power coupled with additional storage.
the Scale-Out vs. Scale-Up in enterprise flash arrays - (architecture ABCs) - a blog by Shachar Fienblit, CTO - Kaminario (May 2014)

"Channels refer to the number of flash chips the controller can talk to simultaneously. Low end SSDs usually have 2 or 4 channels; high end SSDs usually have more..."
SSD Controller Primer #8 - Channels and Banks - by Cactus Technologies

suggested SSD articles on
what do enterprise SSD users want?

how fast can your SSD run backwards? - 11 Key A/Symmetries in SSD design - what they are and why you need to know

Enterprise SSDs - the Survive and Thrive Guide - some simple rules to help you stay on the safer side of the tracks in this maddenly unruly market.

Where are we now with SSD software? - (And how did we get into this mess?)

adaptive R/W flash care management IP (including DSP) for SSDs - what is it? and who does it? This will be a disruptive transition.

The big market impact of SSD dark matter - As Fusion-io found out years ago, and OCZ and STEC are reportedly seeing now - some of the very biggest direct customer opportunities for SSDs aren't the big name computer and storage oems.

2015 SSD market milestones - if you're getting up to speed with the SSD market - lists the most significant products, suppliers and changes which happened last year.

enterprise SSDs - exploring the limits of the market in your head - is about enterprise SSD futurology.

Can you tell me the best way to SSD Street? - I'm like the Old Woman of the SSD Village who talks to everyone that passes through. No wonder I have a unique perspective. It would be strange if I didn't.

comparing the SSD market today to earlier tech disruptions - applying a sense of perspective to what's happening now with SSDs